Outlook 2013: Power conversion opts for reverse swing

IBM has already taken the step, moving from the traditional 12V distribution bus to 44V dc. Supplying the PoL converters for these machines, Picor used a factorised power approach. This employs a two stage conversion down to 1V, but the devices sit close together to avoid significant losses. Today, it is difficult to perform that conversion in one step, but companies such as Vicor are working on it. Claudio Tuozzolo, president of Vicor subsidiary Picor, says: "We see an emerging trend in computing and communications, where you convert from 380V to 48V and from 48V to the point of load in one step." Picor plans to produce dc/dc converters that can take 48V as an input – seeing that as the likely emerging standard given its prevalence in telecom already – and deliver a 1V dc output in one package. Its current offering takes a 36V input. The company is unlikely to be alone, but SoC designers are willing to meet the PoL supply vendors part way by increasing the voltages they will accept and integrating their own voltage regulators to convert down to the sub 1V levels demanded by advanced cmos processes. "If you look at the way that scaling of microprocessors is going, fine grained power regulation and delivery is now omnipresent. You are looking at the use of multiple power domains on chip. The only way to deliver power in an efficient way to use on die voltage regulators," explained Intel engineer Arijit Raychoudury at the 2012 VLSI Circuits Symposium in Honolulu. The Intel team developed a voltage regulator based on digital technology that could generate a range of output voltages from a stable, higher voltage input. On die regulators will make it possible for a processor to take an input of around 3V and produce on chip voltages ranging from 0.8 to 1.2V, where most of these circuits currently operate. Intel's approach uses standard cmos processes, albeit with improved passives such as capacitors and inductors that can be implemented in the thick metal layers above the chip's surface. Some companies are looking at more ambitious process options, using materials originally developed for use in displays and other devices that need thin film transistors because of their transparency and suitability for low temperature processing. At the VLSI Symposium, Renesas and Samsung described approaches based on oxides of different combinations of indium and zinc. Samsung engineer Sanghun Jeon says despite these oxide materials being amorphous, rather than crystalline, they have comparatively high carrier mobility, as well as a wide bandgap and breakdown voltages in excess of 100V. They may not go as far as supporting the integration of high power transistors, but Jeon says: "In conventional power systems, the power management ic and gate driver are separate devices. In our implementation, they are integrated." Using indium gallium zinc oxide, Renesas' engineers have used comb structures to integrate experimental high voltage transistors on top of test chips based on standard cmos logic. Renesas researcher Kishou Kaneko says the process could improve integration in automotive power systems by bring logic and power control together, but systems issues will restrict how far integration can go. Maik Herzog, director of electronic design automation at Infineon, says the company is looking at increasing packaging density and integration in automotive electronics. "The mcus will be separate, but everything else will reduce down to one big system chip," he believes, which could introduce heat management issues when high power designs such as airbag triggers are integrated with control logic. "You could have firing squib controls that get very hot very close to an mcu. Will you know what these big temperature gradients will do to your timing?" For the higher voltage PoL power devices that will be used with renewable energy systems and electric or hybrid vehicles, attention is shifting towards new materials, such as silicon carbide (SiC) and gallium nitride (GaN). Both SiC and GaN have bandgaps around three times larger than that of silicon. Their critical field rating – which leads to higher breakdown voltages – is ten times higher than silicon. Although SiC's carrier mobility is worse than that of silicon, it has much higher thermal conductivity. As a result, SiC devices can run reliably at a junction temperature of more than 150°C, helping to save on heatsink and packaging costs. GaN has better carrier mobility than silicon, but two factors make its use in power semiconductors in the long term less certain. One problem is its much higher wafer cost. In a paper presented at the Conference on Integrated Power Electronics Systems (CIPS) earlier this year, Nando Kaminski of the University of Bremen said bulk GaN wafers cost around €100 per square centimetre, versus €10 for SiC or silicon's €0.10. The improved density of SiC devices, thanks to their higher breakdown voltage and thermal characteristics, is likely to lead to device cost parity with silicon relatively quickly, he claims. Power semiconductor manufacturers can take advantage of a different form of scaling to their digitally oriented brethren: they are making more use of 3d techniques, arranging transistors and protective diodes vertically such that the active region extends through the wafer itself. Diodes and transistors go not just on the top of chip, but also on the bottom. In one design being used by Infineon, a bipolar power transistor goes on the top surface, with the diode which protects it going on the back. Each diode and transistor are made up of hundreds of cells to reduce the resistance through the semiconductors when they are switched on: if not, they will get extremely hot and fail. But the connection between the diode and transistor also needs low resistance. This means using not just lots of parallel vias through the wafer, but also reducing the physical distance between them. The best way to do that is to shave the wafer so it is less than 100µm thick. If removed from a protective case, the foil like wafer buckles. "The stresses from manufacturing make the wafer bend by itself," explained Reinhard Ploss – now Infineon's ceo – at the ISS Europe conference earlier this year. Because of their high raw wafer cost, GaN devices are likely to be fabricated epitaxially on much cheaper silicon wafers, at the cost of crystal defects and overall performance. The use of epitaxial layers means that, in contrast to silicon and SiC devices, the transistors have to be arranged horizontally and these tend to take up more area because of the space needed for contacts. Lateral devices also have trouble sustaining high electric fields, which reduces the voltage that they can support reliably. As GaN is a direct semiconductor, bipolar transistors are problematic because the carrier lifetime is so low. GaN can, in principle, still be used to make power mosfets, but unless SiC runs into trouble, the III-V material is more likely to find its way into high frequency, rather than high power, applications. But further work on materials will help to keep pushing the voltages for high efficiency power delivery up, while cmos logic gradually slides to less than 1V.