The dsPIC33CK has expanded context selected registers to reduce interrupt latency and new, faster instruction execution to accelerate Digital Signal Processor (DSP) routines. The dsPIC33CK single-core family complements the dsPIC33CH dual-core family based on the same core, Microchip adds.
With 100 MIPS performance, the core of the dsPIC33CK delivers almost double the performance of previous single-core dsPIC DSCs, Microchip says. This makes it suitable for motor control, digital power and other applications requiring sophisticated algorithms such as automotive sensors and industrial automation. It has been designed specifically for controlling multiple sensorless, brushless motors running field-oriented control algorithms and power factor correction.
The DSCs are also designed to ease functional safety certification required by many automotive, medical and appliance applications where safe operation and shutdown in failure situations are critical. The devices include integrated functional safety features for safety-critical designs such as: RAM Built-In Self-Test (BIST) for checking RAM health and functionality; Deadman Timer for monitoring the health of application software through periodic timer interrupts within a specified timing window; Dual Watchdog Timers (WDT); Flash Error Correction Code (ECC); Brown Out Reset (BOR); Power On Reset (POR); and Fail Safe Clock Monitor (FSCM).
