The module, the PIM4710PD, offers high current handling of 20A and increased power capability of 780W at the lower end of its input-voltage range with the capability to handle up to 1080W with a 54V input.
The module is compliant with the industry-standard quarter-brick footprint – measuring 57.9 x 36.8 x 21.33mm (2.28 x 1.45 x 0.84in) – and has been optimised to simplify design in blade server applications based on ATCA and PICMG 3.7 systems. The PIM4710PD is intended for server and storage systems in any industrial, telecom and data communications application that employs either distributed power or intermediate bus voltage architectures.
The PIM4710PD integrates low-EMI design techniques to ensure that external filtering is kept to a minimum, meeting the CISPR Class B EMC standards required for deployment in ICT systems. It also offers improved ripple and noise characteristics and a simplified circuit design that delivers reduced component count and system costs.
The module operates over an input range of 36V to 75V, and offers high-power performance delivering a peak of 1080W with a 54V input, 960W at 48V, and 780W at 39V. The PIM also delivers efficiency of up to 98.8% at 780W for the main unit, which results in reduced energy and cooling costs; operating at a typical 15 A output current at 82°C, the module requires airflow of only 1.5m/s (300 LFM).
As with the PIM4610PD, it offers built-in digital monitoring and an extensive range of energy-monitoring functionalities via its I2C/PMBus interface. The module also offers integrated hot-swap functionality and hold-up charge and discharge management. The inputs also include dual power feeds with OR’ing functionality and ‘enable’ signalling.
Protection features of the module include protection against input transients, reverse polarity, over-temperature, over-current, input under-voltage and inrush current.
In addition, enabling the protection of processors and other key silicon devices including FPGAs, the module can be configured to enable a well-controlled shutdown procedure. The feature enables de-assertion of the Power Good pin following input power being below the assigned level.
