Microchip launches low-voltage 64-megabit serial quad I/O SuperFlash memory

DTR gives the ability to output data on both edges of the clock which reduces overall data access time and power consumption. SuperFlash technology reduces power consumption by providing much faster erase times of between 35 and 50 milliseconds, compared to competitive Flash devices which take more than 30 seconds to erase.
The SST26WF064C also integrates a hardware-controlled reset functionality enabling a robust device reset. Most serial Flash devices in the market do not support hardware reset function due to pin-count limitations on the package. With this Microchip device, customers have the option to reconfigure the HOLD# pin for this reset function.
Operating at frequencies reaching 104 MHz, the device enables minimum latency eXecute-In-Place (XIP) capability without the need for code shadowing on Static Random Access Memory (SRAM). It uses a 4-bit multiplexed I/O serial interface to boost performance while maintaining the compact form factor of standard serial Flash devices. The SST26WF064C also supports full command-set compatibility with traditional Serial Peripheral Interface (SPI) protocol.
SuperFlash technology also means the device is based on a proprietary split-gate Flash memory cell giving additional capabilities such as high endurance cycling of up to 100,000 erase/write cycles, data retention of over 100 years and the industry’s fastest erase times.
Developers can begin designing with the SST26WF064C Flash memory by using Verilog and IBIS models as well as device drivers.
The SST26WF064C is offered in a variety of package options including an 8-contact WDFN (6 mm x 5 mm), 8-lead SOIJ (5.28 mm), 16-lead SOIC (7.50 mm) and 24-ball TBGA (8 mm x 6 mm).