Toshiba develops energy saving flip flop circuit
In a bid to reduce power consumption in mobile equipment, Toshiba has launched a new flip flop circuit using 40nm cmos process. According to the company, the device's power dissipation is up to 77% less than that of a typical conventional flip flop. The company also claims it achieves a 24% reduction in total power consumption when applied to a wireless LAN chip.
To achieve this, the company changed the structure of a typical flip flop and eliminated the power consuming clock buffer.
According to Toshiba, the problem of data collision between the data writing circuitry and the state holding circuitry was overcome by adding adaptive coupling circuitry. This reduced the transistor count from 24 to 22 and the cell area to less than that of a conventional flip flop.