Engineering publications brought to you by Mark Allen

Risc v

Ventana Micro Systems emerged from stealth mode after raising $53mn

Edge-computing voice recognition on DSP-capable RISC-V processors

Collaboration looks to accelerate functional safety development for RISC-V

Imperas updates Free reference model riscvOVPsimPlus

Agile Analog joins RISC-V International as a strategic member

RS introduces new automation evaluation and development kits

Andes certifies Imperas RISC-V Reference Models for SIMD/DSP extension

IAR development tools support Fraunhofer IPMS RISC-V processor cores

Embedded Prototyping Platform features PolarFire SoC FPGA

Andes embedded SoC shipments hit 2bn in 2020

SiFive collaborates with Imperas, qualifies models

IAR extends supports for Andes RISC-V processor technology