Engineering publications brought to you by Mark Allen

Verification

Cadence announces DRAM verification solution

Imperas announces RISC-V product updates

Aldec adds UVM Generator to Riviera-PRO

Codasip expands ecosystem with XtremeEDA

Sondrel develops Performance Verification Environment to fast-track ASIC creation

One small step…

Siemens acquires PRO DESIGN's proFPGA product family

Avery Design debuts CXL 2.0 System-level VIP simulation solution

Aldec updates Riviera-PRO with inclusion of OSVVM 2020.08

Silicon Labs selects Imperas RISC-V Reference Model for verification

Pickering Interfaces announces Partner Programme with System Integrators

HES-DVM simulation acceleration flow for Microchip FPGA designs