Engineering publications brought to you by Mark Allen

EDA & Design Software

Achronix using Synopsys' DesignWare IP solutions to accelerate FPGA development

CEVA's DSP and Voice Neural Networks integrated with TensorFlow Lite

Synopsys delivers industry's first Ethernet 800G verification IP

Cadence digital full flow optimisd to deliver improved results

Cadence Tensilica HiFi IP accelerates AI deployment

First verification IP for PHY covering multiple protocols

Cadence makes Integrand acquisition

UltraSoC collaborates with PDF Solutions to prevent in-life product failures

Analogue design will be needed until you or I turn into robots

Standard allows stacked dies in 3D ICs to connect with test equipment

Cadence expands collaboration with Broadcom for 5nm and 7nm designs

RECOM helps engineers design digital models faster