Developed in collaboration with Mentor, a Siemens business, the ML-enhanced DFM solution, built on Mentor’s Calibre nmDRC platform, is able to provide customers with a more effective design and development experience and, ultimately, contribute to a faster time to market.
The DFM kit is launching as an update to the process design kit (PDK) for GF’s 12LP+ differentiated semiconductor solution. Built on a proven platform and production ecosystem, the 12LP+ has been optimised for artificial intelligence (AI) training and inference applications, and is currently ready for production at GF’s Fab 8 in Malta, New York.
GF’s DFM solution is among the first of its kind in the industry and GF plans to roll out the capability to the PDKs of its 12LP and 22FDX semiconductor platforms in Q4 2020.
“We are excited to launch this new enhancement, infused with advanced machine learning models, and provide our customers with a quicker overall DFM verification and an even more effective design experience – all toward the goal of successful prototyping and a faster time to market,” said Jim Blatchford, vice president of Technology Enablement at GF. “Our close partnership with Mentor helped enable the new enhancement to be seamlessly integrated into our 12LP+ PDK, and we look forward to rolling out additional machine learning-infused capabilities in the PDKs for our other specialty semiconductor solutions.”
GF pioneered the DFM checking platform, called DRC+, which combines pattern-matching tools from electronic design automation (EDA) software suited with a proprietary library of yield detractor patterns. DRC+ enables chip designers to preventively detect defective patterns, or hotspots, in early designs that could lead to manufacturing defects.
GF and Mentor have partnered to integrate GF-developed ML models into DRC+, to help amplify the ability of DRC+ to recognize new and previously unseen hotspot patterns and improve production yield. Trained by GF on silicon data collected during its manufacturing operations, the new ML-enhanced DFM kit has been validated and qualified to enable chip designers to more successfully discover and mitigate potential problems early in the design process.
Engineered to meet the specific needs of the fast-growing AI market, GF’s 12LP+ offers an enhanced combination of performance, power, and area. New features include an updated standard cell library, an interposer for 2.5D packaging, and a low-power 0.5V Vmin SRAM bitcell that supports the low latency and power-efficient shuttling of data between the AI processors and memory.
Driving the enhanced performance of 12LP+ are features including a 20-percent SoC-level logic performance boost over 12LP, and a 10-percent improvement in logic area scaling. These advancements are achieved in 12LP+ through its next-generation standard cell library with performance-driven area optimised components, single Fin cells, a new low-voltage SRAM bitcell, and improved analogue layout design rules.
