Engineering publications brought to you by Mark Allen

ASIC & SoC

CDNLive 2009 EMEA

Structured messages ease SystemVerilog testbench debug

Tool boosts productivity

Interconnect is a SNAP

Disastrous Q1 results for STMicroelectronics

Is the writing on the wall for the discrete dsp?

NEC Electronics and Renesas merge

Samsung obtains first EDA tool for statistical memory analysis

DATE 09

Industry’s ‘broadest’ 40nm G physical IP platform

IMEC unveils multiprocessor design tools

Major decline seen in asic design starts