Industry’s ‘broadest’ 40nm G physical IP platform

According to ARM, the silicon validated physical IP enables the development of performance driven consumer devices requiring advanced functionality, without increasing power consumption. The platform has been designed to enable a high degree of flexibility through the multi channel Logic libraries aimed at addressing the leakage challenges of submicron designs. Because the multichannel length libraries are footprint compatible, this allows cell swapping within standard design flows and power savings by replacing the HVt, RVt or LVt implant layers with long channel length devices. Simon Segars (pictured), ARM's executive vice president and general manager, physical IP division, said: "ARM is in the unique position of developing processor IP and physical IP in parallel so they fully complement each other and reduce the overall design cycle. We further enhance our technology through early engagement with the leading foundries and EDA companies to ensure a robust support infrastructure exists, providing the designer with a low risk, silicon proven, cost efficient design strategy. Through our strategic relationship with TSMC we can optimize the physical design with the manufacturing process technology to provide optimal results." John Chilton, Synopsys' senior vice president of marketing and strategic development, added: "ARM and Synopsys are dedicated to reducing design cycle challenges through close collaboration on foundry ready physical IP platforms and integrated design tools. ARM offers designers a comprehensive 40nm offering, and we have been working with ARM to ensure the new platform is validated with our Lynx Design System. Pretesting ARM IP with Lynx's foundry ready system provides a low risk path to a proven, manufacturing-ready SoC solution at 40nm. The combination will deliver highly optimised designs with accelerated, reduced cost chip implementations."