Analogue and mixed signal IP designers face challenges at 20nm

Yet while many roadmaps continue to show a path to 10nm and beyond, there is real evidence that, since the 28nm node, the industry is failing to keep up with the progress anticipated by Moore's Law. And analogue and mixed signal (AMS) designers are facing particular difficulties. In his keynote to last month's IPSoC 2012 conference in Grenoble, Joachim Kunkel, general manager of the Synopsys Solutions Group, highlighted some of the challenges facing analogue and mixed signal IP designers at 20nm. "We have been tracking the adoption of new technology nodes and while it has been fairly consistent up to the 32/28nm node, there is now a noticeable slow down. We have seen a significant change of procedures as customers start looking at 20nm," he said (see fig 1). Chip designers are struggling to overcome the technical challenges presented by the 20nm geometries they need to adopt in order to meet demand for more powerful devices which consume less power. Increasing development costs (masks and tools), packaging issues and design rule complexities are to be expected, but factors such as the scaling of core supply voltages, the impact of double patterning and analysing layout dependencies are beginning to cause headaches, especially for AMS designs. Kunkel intimated that, although difficult, it has been possible to scale down analogue circuits – until the 28nm node. "Now, we are finding they no longer scale in the same way and we are seeing some resistance to moving to the next node. Analogue designers at 45nm were resisting going to 28nm. Some who have gone to 28nm are having a nightmare." Assessing the impact As a leading developer and vendor of IP, Synopsys has had to prove its capability at every new node. It has an extensive range of IP at 28nm, for example, and recently announced a 20nm test chip. This test chip, featuring some 1500 devices integrating such fundamental IP structures such as ring oscillators, DDR4 I/O, analogue IP and test (BIST) circuitry, was designed specifically to assess the impact of the 20nm node on AMS designs. The chip uses double pattern lithography, which imposes stricter design rules than previously. According to a Synopsys White Paper, double patterning means poly and metal density must be kept uniform across the die. Kunkel explained, that at 20nm, it is imperative that designers ensure matched circuits are located in the same density areas on a chip. One example is mosfets at the heart of a d/a converter, which must all be in a uniform density area to ensure performance. Designers are now having to perform density checks across the device and density fills are becoming necessary. Larger AMS circuits used for matching or as decoupling and filtering capacitors, are among the worst affected, said Kunkel. These high gate area devices must be fragmented and distributed to satisfy stricter density rules. As a result, the silicon area for some analogue devices actually increases when migrating to the next node. An example is an audio/video IP block. At 1.3V on a 20nm process, there is no voltage headroom to provide high linearity at a 1.8V supply so, to preserve the same signal to noise ratio, area has to increase significantly. Kunkel said there are techniques that can help, such as internally processing signals with large voltage swings. Issues such as these – including the fact that nominal Vdd is going down as static power is going up (see fig 2) and the contradictory power and speed requirements associated with single ended interfaces –are not only causing customers to hesitate, but also to realise that new analogue architectures are necessary. Another issue with double patterning at 20nm is that device gates must be oriented uniformly across the wafer. Previously, IP blocks could be rotated to better fit the device layout and footprint. Although this started to become an issue at 28nm, when combined with other design and packaging restrictions, losing the ability to rotate IP blocks has made layout considerably more complex. Uncertainty and reliability Two further issues affecting AMS circuits were visible at the 28nm node, but are beginning to compound at 20nm: uncertainty of electrical behaviour; and reliability. This is primarily due to the sensitivity of analogue devices to complex parasitic interactions. Further uncertainty arises from manufacturing variability and layout dependent effects due to geometry, device orientation and distances between devices. Random local variation – such as gate length, diffusion and doping – is now a significant part of total variation and creates layout dimension effects that need to be addressed in the layout phase. Reliability is also impacted by electromigration, which is more prevalent at advanced nodes. This affects interconnects in particular and requires yet more rules and restrictions, including current density limits, further impacting layout and architecture. "We need a new architecture and a new approach to SoC floorplanning for AMS design," Kunkel contended. Synopsys' rival Cadence is reporting similar issues and is also working with customers and foundries to try to alleviate problems. The key, it says, is to ensure design intent is preserved during the design process, rather than leaving verification until after the layout is complete. New software that analyses layout dependent effects, such as resistor/transistor matching, tools that enable electrically 'correct by construction' layout, plus associated methodologies, such as 'electrically aware design', are emerging from leading vendors. Increased visibility into the circuits through BIST has become essential for IP at advanced nodes, while built in self repair (BISR) is becoming more prevalent to address inevitable and unavoidable reliability issues due to the lithography. Layout dependent effects, which used to be second or third order problems, can now cause a chip to fail if they are not taken into account at the design stage, Synopsys warns. At 20nm, IP and SoC designers can only be successful by working in partnership, primarily with the foundry. Kunkel warned this requires a foundry centric view of SoCs, which can be quite different from the designer's view. "At 20nm, there needs to be a much deeper link between layout and circuit design, but the problem is that the system guys are not interested in foundry issues," Kunkel said. Meanwhile, there is a growing expectation that some radical new technology will emerge to save the day. Kunkel remarked that some Synopsys customers who have been looking at 20nm, having heard about new technologies such as FinFETs, are considering skipping the 20nm node entirely. Both Cadence and Synopsys are keeping a close eye on progress with 14 and 16nm FinFETs. But the essence of the problem at 20nm, according to Kunkel, is that you can't just take what you did at 28nm and put it down at 20nm. Railway graphic courtesy of Cadence Design Systems