Bringing better visibility

Embedding test circuitry in silicon is nothing new. For those designing semiconductors, boundary scan interfaces that give access to test IP within the chip are relatively commonplace. So when Xilinx and Agilent launch a new analysis environment for testing serial links in fpgas, why the raised eyebrow? This time, the test silicon and software is not just aimed at semiconductor designers, but also at embedded systems engineers, effectively turning a significant portion of the test and measurement business model on its head. Serial buses are at the heart of the problem. The migration of traditional parallel buses to gigabit speed serial gives the system designer a couple of fundamental challenges. And no longer are these challenges confined to the rarefied realms of telecommunications and defence/aerospace. Before verifying that the data being sent down the serial link is correct, the designer first needs to know whether the transmission medium is working reliably in order to expect the protocol to be correct. Whilst a logic analyser provides a functional tool that can check if the data on the bus is correct or not, there has been a lack of standard routines available to check the transmission medium. Bit error rate testing provides a standard ‘figure of merit’ measurement for digital communications that employs a test pattern generator – generating several different pseudorandom test patterns – at one end of the signal path and a receiver at the other. Whilst bit error rate testers are available that perform bit, word, frame and block error measurements on the received data and present that data in histograms or graphs of BER versus time, they represent yet another piece of specialised equipment on the test bench and one with which the average system designer is unfamiliar.