CPLD flexibility enables wide application

Yet, while we are educated on the benefits and features of parts manufactured on 28nm processes, many applications are served by something simpler – the complex pld, or cpld. The word 'complex' hasn't been used by accident. It was deployed to delineate a new category of device which appeared almost two decades ago; one which sat between the simple pld and the upstart fpga. In a sense, the cpld could be considered the product which technology forgot; over the years, it didn't get very much bigger and didn't find itself undergoing the ritual 'process shrink' experienced by its larger fpga brothers. But it hasn't been the device that designers forgot; billions of cplds have been sold. Now, the cpld is being pushed down the technology curve. Lattice Semiconductor, for one, recently launched the Mach XO2 family, manufactured on Fujitsu's 65nm embedded flash process. Meanwhile, fpga rivals Altera and Xilinx are producing their respective MAX V and CoolRunner II families on 0.18µm processes. Chris Fanning, general manager of Lattice's low density solutions and mixed signal solutions business, said cplds represent around 5% of Lattice's revenues. "But cplds are the fastest growing sector in the company – and we are investing in them." The attraction is obvious; cpld sales are currently running at around $600million a year; the majority shared between Lattice, Xilinx and Altera. Lattice expects to become market leader by the end of 2011, based on projected sales of Mach XO2. Fanning said: "Low density fpgas are now targets for cplds and the XO2 will accelerate our gains in this market." Not only does Lattice have the low end of the fpga market in its sights – devices such as Xilinx' Spartan and Altera's Cyclone – but it also believes there is the opportunity to take business from asic and assp vendors and from discrete solutions. Together, these markets are worth in excess of $1bn a year. Fanning continued: "Most people associate asics with the high end of the market, but at the low end, there's an equal number of asic, assp and discrete solutions, particularly in consumer products. We have learned what customers need and what type of pld will be most effective." Low cost means latest processes Gordon Hands, pictured, Lattice's director of strategic marketing, said one of the keys to market success is cost. "Getting low cost means using the latest processes, so XO2 is made on 65nm, compared to 130nm for the XO range. And we've also hardened some functions in order to save look up tables." According to Hands, MachXO2 devices are being adopted across a broad range of applications, both in equipment types that have traditionally used programmable logic and those that have not. "Telecommunications infrastructure, servers, storage and industrial automation have been traditional users of low density programmable logic. Designers in these industries are using XO2 devices for their next designs, taking advantage of the additional integration, higher logic densities and hardened i2c, spi, timer counter and user flash memory components." But Altera Europe's marketing manager Bob Blake isn't seeing the application area for cplds broadening substantially. "We continue to see the parts being used in such applications as I/O expansion, level shifting and power supply sequencing." But the pld's 'glue logic' heritage is still playing a role. "We're also seeing them being used to take asics and assps to market when companies find design problems," Blake added. Hands, however, sees cplds finding a home in less traditional applications, including portable and handheld devices. "Here," Hands believes, "designers are intrigued by the combination of small package size, low cost and low power. The most common use of the XO2 in these applications is peripheral expansion of the application processor or chipset typically used. While i2c and spi appear to be the most widespread interfaces available from application processors, XO2 devices are commonly being considered for muxing and bridging these serial buses." Blake noted Altera's MAX V cplds were trending towards lower power consumption and smaller packages. "This makes them more suitable for use in hand held devices and we see cplds used extensively in smartphones and portable video players." Moving devices to a smaller process results in a smaller die size. That's all very well, but it creates I/O problems. "Shrinking die area means less room for I/O," Hands acknowledged. "So we have had to implement triple staggered I/O pads and I/O banks which support different standards." Lattice has found that designers tend to mainly use one 'flavour' of I/O. But the problem is that, traditionally, I/O banks have been of equal size. The solution is assymetric I/O banks. "One of the benefits of the cpld is that it offers 'instant on' capability," Blake pointed out. "MAX V devices also blend embedded flash and sram, which offers the same kind of logic structure found in fpgas. Other features include user defined flash memory and built in oscillators; we will have IP to enable digital PLLs in the near future." Power consumption is also important. "Static power is critical," Hands noted. "We have reduced power consumption by a factor of more than 100." This has been achieved by selecting Fujitsu's low power process and by selecting the appropriate transistors for the job. "Parts of the design don't need small transistors," Hands asserted. "This helps power consumption because leakage is proportional to channel length." Lattice is making Mach XO2 devices available in three options – ZE, HC and HE. The ZE option runs at 60MHz from a 1.2V supply. The HC option is a 2.5/3.3V part running at 150MHz, while the HE is a 1.2V device running at 150MHz. The ZE and HC options offer from 256 to 7000 LUTs, while the HE variant offers from 2000 to 7000 LUTs. If that doesn't seem to offer much space, Hands said an 8bit microcontroller can be implemented in 300 LUTs. "A 1200 LUT device can house a Mico8 microcontroller, plus four or five serial I/O, some control logic and a memory controller," he noted. There are seven MAX V variants, spanning 32 to 1700 macrocells and with a choice of packages. MAX V features include a configuration time of less than 0.5ms and a standby current as low as 25µA. They can support lvds communications at up to 304Mbit/s and offers up to 8k of user flash memory. Unlike Lattice, Blake doesn't see cplds impinging on the low end of the fpga market. "The largest MAX V cpld is around 1700 macrocells, while the smallest Cyclone device has some 3000 macrocells. FPGAs are also more feature rich, so suit different applications." The cpld certainly isn't yesterday's technology. "We continue to see what we should be doing for next generation devices and to determine whether more functionality needs to be integrated," Blake concluded.