Altera embeds ARM processors to create ‘distinct class of device’

There was, in essence, nothing new to report at the time; Altera freely admitted that it had been supplying products to the market for many years and the Nios soft processor core for about a decade. But what focused Altera's attention was the degree of take up for programmable logic. Figures released in 2010 by Altera claimed 42% of embedded systems projects used fpgas. And in the latest statistics, Altera says between 25 and 30% of fpgas it ships will accommodate at least one Nios core. Chris Balough, senior marketing director for software, embedded and dsp said at the time that the Embedded Initiative was 'a declaration of additional steps that would allow us to do even more things in the embedded market'. The Embedded Initiative alluded to products featuring ARM Cortex-A9 processor cores and Altera has now put some flesh on the bone with the announcement of what Balough describes as a 'distinct class of devices' called SoC FPGAs that are different enough from current products to warrant their own category on the Altera website. "The embedded systems community has decided that programmable logic within systems is a good idea," Balough commented, "and the community has made this decision on its own. Our approach with SoC FPGAs is to provide the widest set of solutions." The SoC FPGA blends a dual core Cortex-A9 MPCore processor with Altera's 28nm fpga fabric, creating a device which Balough believes offers 'an order of magnitude better performance than is available from Nios'. "A soft cpu, such as Nios," he continued, "can only run so fast. SoC FPGAs have a much higher clock speed and are more complex, which means we needed to harden to core. And the Cortex-A9 core is more than we could do ourselves. Taken together, it's a classic piece of semiconductor integration." Even though Balough believes SoC FPGAs are 'distinct' devices, he admitted they don't stray 'too far from the pack'. "They have been configured to hit a market 'sweet spot'," he noted. "The performance will meet customer requirements, but SoC FPGAs have been designed to maximise the use of the ecosystem." So designers will not only be able to use the familiar Quartus fpga development flow, they will also be able to access the Qsys integration tool introduced last year as part of the Embedded Initiative. And there will also be access to the ARM ecosystem. A further benefit is the introduction of a virtual prototyping platform, developed in association with Synopsys. "We are serving an existing market," Balough said in justification. At the heart of the SoC FPGA is the hard processor system (see fig 1). This comprises the dual core Cortex-A9 MPCore processor, along with a range of peripherals and a multiport memory controller. The hard processor system is tightly integrated with Altera's fpga fabric, which comes in the guise of the Cyclone V or Arria V. This tight integration is said to support a peak bandwidth between the two elements of more than 100Gbit/s. Altera adds there is integrated data coherency between the processor core and the fpga fabric. Because many common peripherals are included in the hard processor system, there is no need to implement them in the fpga fabric; in turn, allowing more custom logic to be accommodated. "The whole idea is to make it easier for designers," Balough noted. The Cyclone V and Arria V based devices both feature a dual core 800MHz ARM Cortex-A9 MPCore processor, along with a NEON media processing engine, single/double precision floating point unit, L1 and L2 caches and error correction code (ecc) protected memory controllers. SoC FPGAs are said to deliver a peak performance of 4000DMIPS and to consume less than 1.8W. The processor system and the fpga fabric are powered independently and can be configured and booted in any order. Once in operation, the fpga fabric can be powered down as needed to conserve system power. "The devices are flexible, because designers will want to start their systems in different ways," Balough pointed out. "Some may need to boot the fpga part first because of PCI-Express components. Others many need to get the processor up first. And designers can make a run time decision about whether to turn off the fpga and save power." Altera has designed the memory controllers in house. "We decided to take this approach," Balough said, "because most dram controllers are oriented either for throughput or for latency; nothing balances the two. Neither are many memory controllers optimised for multipart front ends. This is an example of where Altera needed to get the architecture right." ECC is included, Balough added, because it's getting harder to get reliable board designs at clock rates in excess of 400MHz without it. The Cyclone V and Arria V fabrics include embedded transceivers running at up to 5Gbit/s and 10Gbit/s respectively. There are also variable precision dsp blocks. The Cyclone V variant offers up to 110,000 logic elements (LEs), while Arria V parts have up to 460,000 LEs. With SoC FPGAs targeted at embedded applications, Altera has paid attention to I/O requirements. "We decided to put a lot of dedicated I/O around the hard processor system," Balough said. "But there is flexibility if a designer wants more I/O than is allocated to the hard processor system. If you want to pin out all the peripherals, then you will need more I/O, but for most configurations, the 161 I/O on the smallest part will be fine and designers shouldn't need to use the fpga fabric." It is generally accepted that software now represents the larger part of an embedded systems project and Altera has developed a virtual prototyping platform in association with Synopsys to allow development to get underway ahead of silicon – SoC FPGAs are not anticipated to be available until the second half of 2012. When the devices appear, there will be four Cyclone V and two Arria V based parts offering a range of I/O and connectivity options. "Software needs to be register and binary compatible with the final hardware," Balough noted, "so we've developed a 'shrink wrapped' kit for software developers; they don't need to know about virtual prototyping." According to Balough, it's a matter of opening the box. "Linux will boot in less than a minute," he claimed. "And there's an optional fpga in the loop extension." While Balough admitted that much of the technology in the SoC FPGA and the tool flow is not new, 'this is the first time they have been tied together in this way'. "We've spent a lot of time putting this together," he emphasised. "Altera is setting a new standard through integration," he concluded, "and the innovation is in how the elements have been integrated. There is two or three times more IP than Altera has previously put in a device and that means it has been harder to get it right."