Do engineers know what they like and like what they know?

But is this suspicion true? Looking to explore this issue, New Electronics – in association with NMI – assembled a panel session at the recent Electronics Design Show.

Opening the proceedings, moderator Doug Amos wondered why designers use a particular silicon approach. “Engineers don’t have all the answers,” he said, “and sometimes they don’t have all the questions. It may well come down to familiarity – although there may be a better approach, it’s what the designer knows.

“An engineer might look at the options, but do they have enough time to evaluate them? Is custom silicon too expensive? Do FPGAs use too much power?”

Each panel member was asked to produce three silicon related assumptions and to discuss them briefly (see box). First up was Clive Bunney from Swindon Silicon Systems.

“We live in a digital age, but it’s an analogue world,” he said. “Everyone talks about things like MIPS, but anything you talk to is an analogue interface.

“And people suggest custom ASICs are too expensive, but it depends on the project. They assume ASICs will cost ‘multimillions of pounds’ and so they can’t use them, but that may not be the case because it depends on what you’re trying to do. If you want a small sensor interface which talks to a larger processor system, an ASIC might be appropriate.”

Andy Culmer, engineering director with services company ITdev, said software related design methodologies are being adopted by the FPGA community and pointed out that FPGAs are more than arrays of gates. “The hard blocks in the latest FPGAs perform just as well as the equivalent blocks in ASICs.”

His third assumption was that FPGAs will be replaced by GPUs. “We need a choice between FPGAs and processors,” he contended, “because designers need programmability. Will we still need FPGAs? Yes, they will work side by side with GPUs and CPUs for optimum performance.”

Adam Taylor, e2v’s chief engineer, addressed design assumptions. “People say FPGAs don’t require as tight a specification as an ASIC. They do; you must do this properly otherwise you’ll be battling from day one.”

His second assumption was that FPGAs require less discipline to design than an ASIC. “FPGAs allow you to sleep easily at night,” he contended, “but not on the job.”

Finally, he addressed an assumption that the platform was more important than the design. “You can ask whether you need an FPGA, an ASIC or something like an Arduino, but what you need is the right tool for the job.”

Concluding the opening statements was Richard York, ARM’s VP of embedded marketing. “There is a belief that only SoC companies can build SoCs. But you can build a chip without a design team; many companies do. If you write the specification properly – as you should – an ASIC can fit.”

He also contended that old technology is valid. “There’s a lot of investment on the trailing edge,” he pointed out, “and 90nm is now on its fourth generation with many companies. Older nodes are also getting better.”

His final point was to address a belief that ASICs cost millions. “If you want to build an ASIC test chip,” he said, “it only costs $16,000. Even a 65nm device costs only $42,000. Building ASICs is just another arrow in the designer’s quiver. The answer might be no, but you need to think about it.”

Discussing the assumptions

Moderator Doug Amos picked up on York’s figure for test chips. “Is that number right?” York said the first thing to do is to get a prototype and find out if it meets the spec. “The $16k is the full cost,” he said, “including 30 or 40 samples. Although it doesn’t include your design costs, it’s no more expensive than an FPGA or discrete based system.”

Asked what you got for the money, York continued: “For $16k, you’ll get 25mm2 of silicon capable of running at several hundred MHz.

Swindon Silicon’s Bunney noted the company only designs at 90nm or larger. “The ‘bleeding edge’ isn’t appropriate for high voltage and analogue doesn’t scale in the same way as digital. At 65nm, you’ll get four times more digital circuitry, but very little improvement in analogue.”

ITDev’s Culmer said he had been involved with mixed signal ASICs in the past and had used multiproject runs. “It cost $40k on a 0.18µm process, but we managed to lay out four copies of the design in the available area, then got them resawn, so we ended up with 160 devices, instead of 40.”

Amos asked for a show of hands of those who design chips. “There are a few here,” he said. When he asked who used FPGAs and CPUs, many more responded.

A contribution from the floor pointed out that while prototyping proves the design works, the money only comes in when you go to production. York responded: “You find out whether it’s right and are you ready to commit?”

Bunney noted the cost of high volume manufacture wasn’t ‘orders of magnitude’ higher. “Costs get higher when you test,” he pointed out, “so there are development costs. But if you amortise those costs over hundreds of thousands of devices, that’s not so high.”

The discussion turned to when an ASIC might be appropriate. Bunney gave the example of a sensor interface, where physical constraints mean an ASIC is the only choice. “Mopping up things into an ASIC is one of the key benefits,” he contended.

York agreed: “System integration benefits can be valuable. For example, an 80% reduction in components can cut $50 from the BoM and that pays for itself quite quickly.”

Another contribution from the floor wondered about tool suite and IP costs. York pointed out those costs aren’t relevant. “You’ll use a services company with expertise and the tools,” he advised. “Give them a spec and get silicon back; don’t do anything in between.”

But one attendee was worried about the inflexibility of ASICs. “We generate boards on short time scales,” he noted. “It’s the fear of getting locked into silicon that isn’t quite right or where requirements change. So while we could use an ASIC, it’s all about time to market. What are the timescales?”

Bunney said most foundries have a fixed time from tape out to samples. “Normally, it’s about 14 to 16 weeks. But while multiproject wafers (MPW) are the cheapest route to prototypes, they run on fixed schedules and that could be one every two or three months. You have to allow for that and make sure you tape out before the shuttle runs.

“However, there are other ways of getting devices, including multilayer masksets. While these are more expensive than MPW, they bring more flexibility.”

Amos wondered what were the implications of specification changes. “You have some control over an FPGA, but is this all needed up front with an ASIC?”

e2v’s Taylor noted: “It’s all about getting the specification right. Once you’ve taped out an ASIC, you can’t change things, so some projects in which I’ve been involved have more people doing verification than design.”

Bunney agreed that a good specification was paramount. “You can build some flexibility into the design if it’s in the spec. You have to know what you want because making changes is costly. Spend time up front getting it right.”

Amos steered the discussion towards FPGAs. “How many use embedded processors?,” he asked the audience. About two thirds of them said they did. “FPGAs bring flexibility,” he believed, “and so does software, but does it bring headaches?”

Taylor pointed to increasing levels of abstraction. “I know of a design where there wasn’t a single line of VHDL; it was all done in Matlab. But how do you verify that?”

York also reported that a piece of hardware had been developed by a Taiwanese company without a single hardware engineer being involved. “It was all written in OpenCL,” he said, “and mapped. While you still need hardware engineers, defining systems through the software they will run is the way forward.”

Amos wondered whether VHDL knowledge is needed nowadays. Taylor wondered whether testbenches could be written in C. “It comes down to working out where you need to invest your effort and when a design is ‘good enough’.”

Culmer said it pays to understand what the code is being translated into. “Having a hardware background is useful,” he contended, “particularly when you need to drop in a VHDL block and instantiate it.”

Summing up, Amos said: “We’ve had some good questions and great observations. We hope you will now go away and test your assumptions.”