Evolution revolution

Software, rather than hardware, stole the show at this year's Mobile World Congress, held last month in Barcelona. While hardware's continual advance is taken as a given, the reward for such endeavour is limited. Software, by contrast, is driving the mobile industry. Xilinx' design platform for the Long Term Evolution (LTE) mobile standard, detailed at the show, exploits hardware and software to benefit cellular equipment makers. The platform, addressing the network's physical layer, uses Xilinx' Virtex-6 fpgas. And using the fpga program load – software – the design platform can accommodate the latest protocol developments while delivering enhanced wireless capacity and algorithmic performance. Xilinx' design platform is targeted at enhanced LTE basestations called Evolved Node B, or eNodeB. It comprises two Xilinx cards: a multimode radio digital front end that, on one side interfaces to the radio's power amplifier and antenna, and on the other, to Xilinx' second baseband channel card. The channel card, in turn, interfaces to a Wintegra network card for connection to the mobile backhaul network. The network card uses Wintegra's WinPath3 access processor. "[System vendors] will not take our platform to production, but will use our silicon and parts of the reference design," said Manuel Uhm, Xilinx' director of wireless communications. As well as LTE cellular basestations, the reference design can also be used for femtocell development: equipment deployed within enterprises and homes to improve wireless coverage and offload traffic from the cellular network's air interface. Isn't the LTE reference platform late, given mobile operators are deploying LTE networks this year while leading wireless equipment vendors already have basestations carrying live traffic that can be upgraded to LTE using software only? "If this was the first time all this functionality was available, then I'd agree," said Uhm. "But we're [designed] in every major LTE rollout in the world right now." The Virtex-6 based reference platform enables vendors to continue upgrading their designs, said Uhm. For example, Xilinx' first implementation of the turbo decoder, a key processing task of the LTE radio channel decoding, supports a 150Mbit/s bit rate. For proposed LTE enhancements based on a 20MHz channel and a 4x4 multiple input, multiple output (MIMO) antenna, the turbo decoder must handle bit rates up to 272Mbit/s. "Our latest generation turbo decoder can support that," he said. MIMO technology enables an end device to either receive multiple data streams, boosting data throughput, or copies of the same signal to tackle poor radio channel conditions. For the radio digital front end card, Xilinx has crammed the required functionality onto one fpga. The digital front end comprises the Common Public Radio Interface (CPRI) and the upstream and downstream functions that are on the digital side of the digital to rf conversion. CPRI is an interface that decouples the front end from the basestation baseband design. Vendors have greater freedom in choosing the two designs they use, while the interface enables the front end to be moved closer to the antenna, improving signal quality. Signal processing tasks include digital up conversion, crest factor reduction and digital predistortion, while downstream tasks include multichannel digital down conversion. Xilinx has integrated the CPRI serdes and framer, as well as the digital signal processing for 2x2 MIMO LTE, on a Virtex-6 LX75T fpga. Xilinx claims this reduces the chip count from seven to one and the power consumption from more than 10W to 6W. According to Uhm, the larger LX130T fpga is needed to support a 4x4 MIMO LTE digital front end. Xilinx has also reassigned the role of the fpga for its baseband channel card. In traditional cellular baseband architectures, vendors use a network processor, dsp and fpga coprocessor. The network processor performs such tasks as the media access control scheduling and radio link control, the latter performing segmentation and concatenation of header compressed IP packets. The dsp performs the physical layer processing, while the fpga executes computationally intensive tasks such as turbo decoding and fast Fourier transforms. In a 10MHz channel, single antenna LTE system, the dsp must execute quadrature amplitude modulation (QAM) processing at 7.2k symbols every millisecond. The resulting bit stream fed into the fpga for turbo decoding is 553kbit/ms. Thus, more than half a megabit of traffic per second must be transferred between the fpga and dsp. That takes up 22% of the available processing time with data transfer, says Uhm. Nor is this LTE example the most demanding: it uses 16 QAM, but 64 QAM can be used. "This is the crux of LTE: the bandwidth has gone up and the latency has gone down," said Uhm. "You need to process much more data in less time." Xilinx' approach to solving the overhead is to bring the dsp tasks within the fpga. For a three sector traditional cellular basestation design, three dsps would be used for the uplink and one for the downlink, with one fpga performing the coprocessing tasks for all three sectors. In contrast, Xilinx' baseband channel card uses the WinPath3 as the network processor and three Virtex-6 LX130T fpgas, each performing all the processing of each sector. "The LX240T can be used instead [of the LX130T] if more MIMO processing is used," said Uhm. Xilinx' functional blocks for the LTE baseband design are in various stages of development. It has completed logic blocks for the FFT, MIMO and turbo code decoders, while it is developing other components such as the remaining functional blocks needed for LTE channel decoding. "Most of the PHY is complete, including the channel decoder," said Uhm. "The portions that are incomplete are generally those where infrastructure vendors choose to differentiate." End users can customise the parameters and get a corresponding net list, with bit accurate C code for simulation use. "We supply the QAM demodulator as source code as the customer may want to tweak it," said Uhm. Certain functions like the turbo decoder are fixed. "It's bits in, bits out – there is no added value here," said Uhm. Yet Xilinx has no intention of developing other functions where system vendors use their IP for platform differentiation. The hybrid ARQ buffer and controller – a mechanism used for robustness against errors – is one such example. Will Xilinx be able to use fpgas for the next cellular development: LTE Advanced? LTE Advanced enhances air interface performance by adopting 8 x 8 MIMO and expanding spectrum usage to 100MHz. In addition, networking developments such as collaborative techniques between basestations, are being developed. "LTE Advanced's 100MHz of channel bandwidth would require considerable more processing but it could be done using fpgas," said Uhm. While work is continuing on the standard's development, Xilinx has yet to start its internal development, although it expects to do so soon. When might an LTE Advanced target platform design be available from Xilinx? "Maybe two years from now", Uhm concluded.