"It is not always in the customer's hand," said Deepak Boppana, senior strategic marketing manager at Lattice. "Standards keep evolving and that can be difficult to match with an ASIC."
Boppana cites chipsets used for small cells as an example. Operators use small cells to extend wireless capacity and improve indoor cellular signal coverage.
Interfaces used by the small cell's chips continue to evolve and an FPGA allows the use of a programmable hardware resource to accommodate change. The FPGA can also be used to solve challenges that may arise with a system that cannot be solved by the ASIC or software alone.
But Dr Nick Johnson, CTO of small cell vendor ip.access, says that if he saw an FPGA in a small cell design, he'd be asking some hard questions of the designer.
"Much of a design involves working closely with SoC vendors," said Dr Johnson. "We expect them to provide the scope for systems, standards and applications flexibility within their devices."
Lattice's ECP5 family comprises six FPGAs, with logic resources ranging from 25,000 to 85,000 look up tables. Three of the devices also have either two or four serialiser/deserialisers (SERDES). The family complements, rather than replaces, Lattice's existing ECP3 FPGA family. While the ECP3 family has greater logic resources – up to 150,000 look up tables and 16 SERDES, for such applications as bridging and switching – ECP5 fpgas are aimed at high volume applications. In addition to small cells, Lattice cites video systems, broadband access, microservers and optical modules. "For high volume, cost is important, as is power consumption and a small form factor," said Boppana.
Lattice says the 40nm CMOS ECP5 family has twice the functional density of competing 10 x 10mm FPGAs implemented in 28nm CMOS. "We have taken a ground up approach to make the die size as small as possible," said Boppana. This involved redesigning the digital signal processing, SERDES and I/O logic. Lattice says competing devices don't match the ECP5's efficiencies as their designs are slimmed down versions of higher end FPGAs.
The ECP5 family delivers a 40% cost reduction and a power consumption reduction of 30%, compared to competing FPGAs, says Lattice. The static power consumption of each function has been reduced, while dynamic power management techniques have been added, such as placing the I/O and SERDES in standby when idle.
The ECP5 family offers up to four SERDES, supporting data rates ranging from 270Mbit/s to 3.25Gbit/s, whilst DSP performance has been enhanced. The DSP memory runs at twice the frequency of the input signal, such that an input signal clocked at 150MHz enables 300million MACs. Lattice has also introduced pre adder logic that halves the multiply operations needed for digital filtering. The enhancements boost the DSP processing performance by a factor of four. "Two hundred multipliers using the ECP3 is equivalent to 50 multipliers on the ECP5," said Boppana.
For small cells, a typical chipset comprises analogue and digital front ends and a baseband processor ASIC.
The analogue front end interfaces to the handsets via an antenna and includes A/D and D/A converters. The digital front end performs digital down conversion, digital up conversion and digital waveform shaping such as crest factor reduction (CFR) that limits the signal's dynamic range.
The baseband processor – comprising a general purpose and a DSP core – implements several tasks: the low level interleaving of data; Layer 2 wireless techniques for sending and receiving data and forward error correction; and the higher level tasks of starting and ending a call, small cell maintenance and overseeing network interface protocols. The baseband processor, at the far end of the radio signal chain, uses Ethernet to connect the small cell to the network (see fig 1).
Boppana says the interfaces used to connect the A/D and D/A converters to the digital front end continue to evolve, from low voltage differential signalling (LVDS) to the JEDEC JESD204B serial interface and the JESD207 that connects the front end and the baseband processor. "There is churn in the data converter interfaces," said Boppana. "It is not the ASIC [baseband processor], but the components around the ASIC."
Another interface is the Common Public Radio Interface (CPRI) that interfaces to the baseband SoC. Adding an FPGA alongside the chipset enables the interface standards and evolutions to be supported.
Cellular operators also have market dependent multimode and multiband radio requirements. "One ASIC may not be able to do them all and you can't go back and a redesign for each," said Boppana.
If an operator supports LTE alone, an LTE chipset will meet the requirements. "But if the operator also requires 3G and Wi-Fi, you can't go back and redesign the ASIC for each," he said. The CFR algorithm used for LTE, for example, differs from the CFR technique used for 3G. "The ASIC may not do both; so you can use the FPGA to do the one for 3G," said Boppana.
ip.access' Dr Johnson points out that makers of larger cells use FPGAs to mop up key product functions, prior to larger scale integration or as part of the final product. But the performance, price and power consumption requirements for small cells means the functionality should be integrated on chip, driven by software. "If we need extra devices to implement an algorithm," he said, "then design a better algorithm."
The ECP5 is also finding use for video processing for applications such as surveillance and video conferencing. The FPGA has sufficient resources to interface to the image sensor, perform such tasks as video deinterlacing, scaling and signal processing before outputting the processed video over a Gigabit interface.
A further market for the ECP5 is to add 'intelligence' to the small form factor SFP optical module (see fig 2).
OE Solutions and AimValley have codeveloped what they call the Smart SFP. By adding logic inside the SFP optical module, operations, administration and maintenance tools can be added to enable services such as Carrier Ethernet and to ensure levels of performance previously agreed between the network operator and its customers are met.
"We have an ECP3 today in an SFP design," says Lattice's Boppana. With the ECP5 devices, extra functionality is now available as well as power consumption benefits.
An AimValley spokesperson would not comment on the technology it uses, but said that adding logic to the SFP enables system and network functions to be performed that otherwise would be implemented in 19in 'pizza boxes' or larger platforms. "There are indeed power consumption challenges in an SFP module, but these can be addressed," said the spokesperson.
