High performance computing comes to the military embedded market

To meet the real time needs of these applications, HPC technology is migrating to ruggedised, compact packaging that meets the size, weight, power and cost (SWaP-C) constraints of deployed military platforms. The result is High Performance Embedded Computing (HPEC) systems that can be built using open standard OpenVPX modules and deployed in standard military system chassis. Embedded COTS vendors are now aggregating and packaging the heterogeneous HPEC environment – comprising single board computers (sbcs), fpgas and general purpose gpus (gpgpus) – to meet the needs of these advanced applications. The benefits of HPC type technologies, developed originally for enterprise back office environments, are being brought to the military environment, thanks to COTS packaging and integration techniques. In essence, it is now possible to take supercomputer levels of processing performance – that, only recently, required rooms full of equipment – and migrate that to rugged open standard 3U and 6U OpenVPX boards integrated into a 19in deployable rack. Application example HPEC allows the compute technology and performance levels typically associated with HPC to be applied to the most demanding processing problems using open architecture rugged hardware. A key element of these systems is high performance interfaces, such as Serial RapidIO and PCI Express. One recent application that serves as an example of how HPEC brings HPC technology into traditional embedded defence and aerospace applications space is a situational awareness system that combines clusters of gpgpus, Intel processor based sbcs, Intel processor based dsp modules and leading edge commercial fpgas to deliver real time visual sensor information into helmet displays. In this HPEC system, data from the platform's external visual sensors (which may comprise a wide number of different sensor types) is aggregated and, depending on which direction an individual user's vision is oriented, the system can deliver the appropriate visual data to that user's helmet display with smooth, realistic imagery. This challenging application requires several teraflops of processing power and many gigabytes per second of bandwidth. This represents levels of performance that were essentially unachievable in a SWaP-C constrained platform as recently as two years ago. GPGPU technology, now with 240 cores in a single processor, has become increasingly dense and delivers significantly improved power/Watt, making these processors – originally designed for graphics and game applications – more attractive for rugged embedded situational awareness applications, such as this vision system. This HPEC system uses a combination of Intel and Freescale general purpose processors, as well as fpgas with Serial RapidIO (SRIO) interconnects between the different modules. SRIO is an ideal fabric for an HPEC architecture because, while it looks very much like high speed Ethernet or Infiniband connections to the general purpose processors, it provides a low latency, high bandwidth interconnect that fpgas can use to stream data directly into the processors. In this system, the gpgpus provide data processing and data stitching between the sensors, while SRIO enables the sensor data to be sent directly into each gpgpu to handle the visualisation streams in parallel and perform processing functions such as pixel correlation. The HPEC system's sbcs manage the SRIO interconnects, the fpgas handle the application's demanding algorithms and the gpgpus handle the sensor data analysis. Using today's embedded boards, such a system can be deployed in multiple compact rugged racks and might comprise up to 18 6U OpenVPX boards. More than half of these would be gpgpu processor boards, delivering in excess of 7Tflops of compute power. OpenVPX enables the gpgpus to be connected in a point to point fashion and SRIO, which provides the OpenVPX data plane bus fabric, handles interconnects to all the subsystems. Advanced second generation Intel Core i7 based OpenVPX dsp boards, such as Curtiss-Wright's CHAMP AV8, are a good match for gpgpu processors, which are typically Intel based. IDT's PCI Express to SRIO bridge chip enables these Intel based boards to communicate using SRIO. Common building blocks Radar, comint, sigint and situational awareness systems access the same key building blocks and can appear quite similar at the component level. The base HPEC platforms developed for applications such as situational awareness are likely to be adapted to address many other types of defence and aerospace SWaP-C-constrained opportunities because they can deliver a large amount of computing power in a very small space. As the types of sensors used on military platforms become more generic, an HPEC platform can serve as the central processor which, when coupled with the appropriate software, can be used to satisfy many different mission requirements. To bring HPEC to the military market Curtiss-Wright has developed individual HPEC components so that system integrators can scale their HPEC system to any level the application requires. Today, system builders can access 5GHz (about 500Mbyte/s) per serdes connection, with 16x5 serdes connections on one module. Curtiss-Wright expects to see a migration to 10GHz serdes in the near future. As fpgas continue to get faster – they are expected to exceed 10GHz serdes – the market will start to look at faster transmission approaches, such as fibre optics. As these processors feature more cores, the ability to cool the components becomes ever more challenging. For rugged deployed HPEC systems, OpenVPX boards cooled with air flow through technology will make it possible to bring these higher performance technologies into space constrained applications. Embedded radar/comint/sigint/situational awareness HPEC systems are designed to handle large amounts of streaming digital, optical or analogue data. To handle this data, HPEC systems use fpga technologies as high speed sensor inputs. FPGAs provide high speed interfaces, not only to the backplane, but also to standard FMC mezzanine card (VITA 57) interfaces. This rich set of high speed I/O integrates into a SRIO dataplane. SRIO provides an ideal sensor interface into scalable large HPC clusters. The SRIO dataplane interface can reside on the backplane or it can be wired between boxes, so customers can scale the system to whatever size necessary for their application. This approach enables customers to select the number of SRIO enabled COTS OpenVPX processing elements needed to support the appropriate amount of sensor inputs for their application, rather than having to build all system components from scratch. Continuum HPEC certification To help support the use of HPEC systems in demanding military applications, Curtiss-Wright has established the Continuum HPEC Certification process. This process of testing and ongoing product management not only ensures the interoperability of each hardware module in an HPEC system, but also that modules are architected with feature sets aimed specifically at operating within HPEC systems. Under the scheme, key enabling software components are supported, board support packages releases are coordinated and regression tested at least twice per year. All modules are validated using a HPEC test suite to ensure functionality in large node systems with demanding data flows. William Pilaud is Continuum HPEC systems architect with Curtiss-Wright Controls Embedded Computing.