Is new standard a plus?

Since the 1990s, many industrial embedded computer systems have been built around the CompactPCI specification, developed by the PCI Industrial Computer Manufacturers Group (PICMG) as a high performance version of the desktop PCI specification. Featuring rugged 3U or 6U Eurocard formats and twice as many slots as desktop PCI, CompactPCI offered a packaging scheme much better suited to use in industrial systems. However, CompactPCI is proving inadequate for many applications as it provides no serial interfaces via the backplane. In addition, the interface chipsets that support the parallel PCI bus will slowly, but surely, become obsolete in the next few years. Compact PCI Express – originally planned as the successor to CompactPCI – also lacks support for SATA, USB and Ethernet and does not provide enough rear I/O connections. A special bridge slot is required for backwards compatibility with CompactPCI. To address these and other limitations, PICMG is developing CompactPCI Plus, intended to be more flexible and cost effective, while providing a migration path that will enable continued use of the CompactPCI ecosystem. Backplane architecture High priority has been given to cost effectiveness and modularity. The architecture is star configured, without a separate hub slot and without management. The central star point is the cpu slot. While neither coding nor management are necessary, these functions are not ruled out and can be added at any time if the application calls for them. The necessary contacts in the connector are reserved, so future expansion can be implemented. Similarly, all protocols are available simultaneously on the connector, on the cpu slot and on the peripheral slots. No contacts in the connector have alternative uses and none is used for multiple functions. While this reduces costs, it also facilitates modularity and, above all, flexibility. The main benefit lies in the universality of the peripheral slots; they are all the same, regardless of whether communication is via PCIe, Ethernet or USB and whether or not a storage medium is inserted. The cpu slot, as defined by CompactPCI Plus, offers support for: • Seven PCIe lanes (4x) • One PCIe lane (16x), for graphics or general high bandwidth use • Eight differential PCIe clock outputs • Eight SATA ports • Eight USB II ports (one differential pair per port) • Eight USB III ports (two differential pairs per port) • Eight Ethernet 10/100/1000BaseT ports. This allows eight peripheral slots to be supported, each with signals present simultaneously. This, in turn, enables standard backplanes to be factory configured; important for small batches or prototypes. If the chipset used can configure the 16x link as four 4x links, then up to 11 slots with 4x links can be connected to the cpu without a switch. Should 11 slots not be sufficient, and if data throughput is not too high, up to 44 slots can be configured as 1x links in one system, if the chipset permits. Even with a 1x link and PCIe GenII, the data transfer rate of 500Mbit/s is twice that of a CPCI 66MHz/64bit system with a maximum of four slots – probably sufficient for almost all uses. The limitations are, more realistically, mechanics and length of the electrical lines, but 20 slots can be realised. And where a switch is still required, the fat pipe slot with the 16x link can serve as a bridgehead. The choice of connector system and distribution of signals on individual connector blocks allows a bridge to be inserted from the rear without loss of slots and without electrical complications. Connector system The connector system for CompactPCI Plus had to satisfy a number of key development goals, the most important of which were: a bandwidth greater than 10Gbit/s; high signal density; a sufficiently wide routing channel between the pins; the ability to carry 1A for the power supply; short press in pins for rear I/O from both sides of the backplane; and mirror symmetrical layout of signal pins and/or no predestination of signal/GND allocation. The high data rate for the connectors is necessary for the future viability of CompactPCI. While such high data rates are rarely needed in industrial computing, the demands of future applications are unknown and it is essential that the connector does not become a system bottleneck. A further requirement was that a sufficiently high number of differential pairs be made available on a 100mm Euroboard. The width of the routing channel – the clearance between the drilled holes for the connector on the backplane – has a major influence on routing and affects the number of layers required and, hence, cost. This is contrary to that for higher signal density, so the correct balance has to be struck. The highest possible current carrying capacity for the signal pins is necessary so that power can be supplied via the signal connector. This means no separate power connector is required, which cuts costs and affords more space for signals on the 100mm Euroboard. Smooth transition As CompactPCI and CompactPCI Plus are neither mechanically nor electrically compatible, the draft PICMG 2.30 CPLUS I/O specification has been developed to create a smooth migration path from CompactPCI into the future of the serial protocol. The cpu defined to this specification acts as mediator between the old and new worlds, linking the conventional, parallel 32bit CompactPCI bus with the new slots, defined to CompactPCI Plus for the serial protocols. With both cpu and backplane defined to PICMG 2.30 CPLUS I/O, the cpu provides the serial SATA, USB, Ethernet and PCIe protocols via the CompactPCI P2 connector, and the backplane links these signals from the P2 connector to the CompactPCI Plus peripheral slots. Figure 1 shows an example of a hybrid backplane for migrating from the conventional slots, supported by the parallel PCI bus, to pure serial CPCI Plus slots. Unlike CompactPCI, the peripheral slots require only a relatively small, low cost connector with six rows of contacts to carry power, high speed signals and any necessary monitoring and control lines. The use of such hybrid backplanes means it is not necessary for 'old' CompactPCI boards to be redesigned; they can be produced for as long as the chips for the parallel PCI bus continue to be available. New designs should, however, be drafted on the basis of CompactPCI Plus. CompactPCI Plus and MicroTCA How does CompactPCI Plus compare with MicroTCA? CompactPCI Plus is primarily aimed at existing CompactPCI users, who may require higher data throughput or additional features such as direct communication with SATA, Gigabit Ethernet or USB. The specification is designed to be the successor to CompactPCI, providing a smooth migration path and allowing CPCI and CPCI Plus to be mixed in a single system. MicroTCA is a new specification optimised for redundancy, high availability, remote management and multiprocessor configurations. Its small form factor could be a key issue for some designs but, if cost is the overriding consideration, CompactPCI Plus would be the better option in most cases.