Leaving a legacy

Almost inevitably, the focus falls on the 'bleeding edge' when discussions turn to fabrication technology. And it's no surprise; the 'bleeding edge' represents the bow wave of the progress of Moore's Law. Riding this bow wave, like some kind of technology surfer, are companies such as Intel, which is producing its latest microprocessors on 40nm lines, and the programmable logic giants Altera and Xilinx, again in production at 40nm. Yet, while some designs are being created and taped out at such nodes as 28nm and 40nm, far more are being targeted at what could be considered to be 'legacy' processes. Douglas Pattullo is director of field technical support in Europe for leading foundry TSMC. He said TSMC has an annual capacity equivalent to 10million 8in wafers. "Some 70% of that capacity is used for process nodes of 0.13µm and greater," he claimed. "Within that total, we shipped 2m 8in equivalents at the 0.18µm node." So, with nodes such as 0.18µm described by Pattullo as 'very important', what happens to a legacy process once it moves away from the leading edge and how long might its life expectancy be? The answer is quite some time. Gareth Jones, director of business operations, Europe, for TSMC, said: "We have some products for original logic, but most are mixed signal, rf or feature embedded flash. We are also starting to see high voltage products being made on what can be described as 'legacy' processes. And our 0.15µm and 0.18µm processes are also being used to produce cmos image sensors." In the end, it all comes down to that old favourite of the semiconductor industry: the road map. Pattullo explained: "When we talk about the leading edge, we're always looking at smaller and smaller features." That road map is taken care of by Moore's Law; TSMC and all other manufacturers know what the next process node will be and when it will be available. "But each process node also has its own road map," he continued. And, of course, different processes suit different applications. "If you're designing a baseband chip, then smaller processes are ideal. If you're doing an audio application, the best technology is something more like 0.18µm; there's no advantage in doing it on 40nm." Pattullo continued: "Of course we have a headline road map showing where the leading edge is going, but we also have an application road map that shows how legacy technologies continue to be developed. If you look at applications such as audio, MEMS or automotive, then you'll see the road map is at different stages. Older technologies are developed by adding more and more derivative modules." Jones added: "TSMC has dedicated teams looking at what derivatives to add to these processes and when." While it may seem somewhat academic, access to legacy processes is an important issue for many companies developing semiconductor products in Europe. "It's quite a European topic," Pattullo noted, "particularly for mixed signal, rf and automotive applications. Companies working in these areas are accessing N-2 nodes (where N is the leading edge and N-2 is two nodes behind) for many applications. It's the sweet spot and sometimes that could be N-3." Is TSMC's 0.18µm cmos process today any different to the one which was launched in 2001? "It's basically the same," Pattullo accepted, "with the same design rules. But we have made incremental improvements." These improvements filter down from lessons learned at the leading edge, where ways are found to optimise manufacturing further and to improve yields. "But the main difference," Pattullo continued, "is the availability of embedded flash, high voltage and similar modules. Each of TSMC's offerings is being improved." He gave an example. "We added the rf module to the 0.18µm process a couple of years ago. In its original format, it offered 1fF capacitors, but we have since added 2fF caps. That means designers can come up with more area optimised solutions while maintaining compatibility with the original design rules." In his opinion, all these moves are being made to optimise area, reduce cost and reduce power consumption. But Jones noted another potential area. "We may also be expanding the IP portfolio in order to apply some of the things that have been learned from more advanced technologies. One example is the redesign of I/O pads." The ecosystem also improves. "IP gets better," Pattullo continued, "and modelling has been validated by many applications. All this means there's more chance of the design being right first time in an older technology." Updating legacy processes may become a legacy in its own right in the future. The reason? Simply that times have changed. Jones noted: "The 'bleeding edge' process used to be driven simply by logic. That's not the case today; modules have to be available at the same time." Pattullo explained. "If you look at the spread of process technologies and think of it as a triangle – logic first, then derivatives – that's wrong because we would never get to optimise processes. If we know that we are going to add, for example, an rf module, then we have to optimise that module for noise and so on from the start. "There's a plan that lays out when modules will be added and they are designed in such a way that we can do the things that improve, say, rf performance are fixed when the core logic process is released. Ten years ago, that wasn't such a requirement." Legacy processes are also an attractive option – particularly for European designers – because the NRE is much lower. "N-2 or N-3 processes are suited to less integrated products and the NRE for a 0.18µm product is a fraction of the cost of a leading edge process," said Pattullo, "and that includes tools, mask sets and IP. If you have a product that is going to run to tens of thousands, it may be better to use an older process and still get the performance you're looking for." The ecosystem for legacy processes and derivatives is becoming increasingly important. "Those at the 'bleeding edge' have expertise and there's a standard set of deliverables. With legacy processes, we need to support small customers on more complex derivative technologies and they often need design kits, stats models, IP and so on. It's important we recognise that it's different and the needs of customers are different." If you have even more conservative tastes, then TSMC can accommodate you. "We've been running a 6in fab for more than 10 years," Jones pointed out, "and while there's still a commercial requirement, then we'll continue to support it." Products being manufactured on this line are generally using design rules of 1 or 2µm. "A lot are simple applications," Jones noted, "like clock recovery chips. Nevertheless, we are still receiving tape outs for the 6in line."