Modelling parasitics in sub-micron IC designs

Such designs comprise more devices and the devices are smaller, leading to more congested interconnect and more difficulty in isolating wires. As wires in an IC get narrower, resistance along them increases. Foundries compensate for this by making the metal layers thicker, as depicted in the blue and grey metal layers in Figure 1. With this change in the aspect ratio of the metal, interconnect coupling increases relative to device performance. Lateral capacitance can build up, as indicated by the taller, thinner Metal 2 wires shown in Figure 2. Vertical capacitance between Metals 1 and 2 and between Metals 2 and 3 has long figured in the calculations of IC designers and has been easy to identify in larger process sizes using common extraction tools, but intra-layer capacitance becomes of greater importance than inter-layer capacitance as process size shrinks below .25µm. Higher operating frequencies and lower voltages also intensify this effect. While some capacitance is natural and limited, lateral capacitance often brings unintended consequences in high density chip layouts. A change in state in a very noisy Metal 2 node may result in an unexpected state change in a sensitive Neighbour Metal 2 node. Also, capacitance of any type loads down the node, requiring more time and power for the node to change state. Thus, the amount of parasitic capacitance on the node can have significant effects on events that are sensitive to time constants, such as signal propagation. Experienced designers route sensitive nodes separately from noisy nodes, keeping them apart or placing shields between them. In larger process sizes, the area of influence is relatively small, so careful prevention is often sufficient. However, at smaller process size, it is risky to rely solely on this approach because nodes are so much closer together. Also, the process of keeping noisy nodes separate from sensitive ones may be unnecessarily conservative, costing space in the design and time in the layout process. Several tools allow designers to extract vertical capacitance to ground from the layout, essentially a process of extracting the area and perimeter of the net and estimating a load capacitance based on that. This simple, low cost process simulates some of the parasitic effects and results in a basic loading amount that protects against simulating faster than the circuit will actually perform; however, it does not account for shielding, crosstalk, lateral capacitance or interconnect resistance. Designers may also roughly estimate the resistance in a potentially troublesome interconnect: "It runs 500µm and is .5µm wide, so that's about x ohms." They manually update the netlist with the resistance and re-run the simulation to ensure it still works. The process is similar for estimating crosstalk or any other effects not covered by extracting lumped capacitance to ground. However, there are many disadvantages of this time consuming and often subjective technique: from relying on the designer's ability to anticipate all of the problem areas in the IC, to overlooking a sensitive net next to a noisy one, to underestimating the parasitic load between them, to the risk of sending an error filled design to the foundry. It can suffice for a few relevant parasitic interactions, but if nets are interacting in a widespread manner, then the 'back of the envelope' approach becomes untenable. At best these approaches may help extract parasitics but at a potential cost in chip performance, silicon size and power consumption. The more reliable method is with a parasitic extraction tool. Such a tool should: * Integrate smoothly with layout, verification and simulation workflow * Reduce the amount of guesswork and estimation in finding problematic parasitic effects * Extract netlists of devices and parasitics, including vertical and lateral coupling capacitance and interconnect resistance * Enable the designer to run a simulation with confidence that parasitics are accurately modelled * Allow the designer to optimise the mix of speed and accuracy in modelling An example of a layout-to-circuit parasitic extraction tool for submicron IC design is the HiPer PX from Tanner. This enables designers to model circuits in 2D or 3D, extract netlists containing interconnect parasitics, and include those netlists in simulations to calculate delay and circuit behaviour accurately. It also automates the task of discovering and modelling parasitics on any cell at frequent points during layout rather than waiting until the end of the project, when it becomes expensive to address problems. The option of 2D or 3D modelling addresses the trade off between the accuracy of the model and the amount of time needed to generate it. 3D modelling is more accurate and better suited to small circuit blocks (<5000 transistors); 2D modelling takes less time and affords reasonably accurate interconnect models in large circuit blocks. The number of nodes in the resulting netlist – devices plus numerous resistors and capacitors due to the finite element interconnect models – can slow simulation unacceptably, so HiPer PX supports netlist reduction. Designers can specify the maximum frequency of interest for the circuit and the tool will simplify the model while guaranteeing accuracy in the simulation up to that frequency. For example, Figure 3 depicts an original layout in a circuit and Figure 4 the parasitics in the circuit modelled as resistors and capacitors. When the designer applies netlist reduction and specifies a maximum frequency, HiPer PX merges resistors and capacitors throughout the circuit and models them as shown in Figure 5. Specifically to model crosstalk, HiPer PX can extract vertical and lateral coupling capacitance between nets to allow simulation of crosstalk, rather than folding that capacitance to ground. Where crosstalk is not a concern, HiPer PX also has a mode to lump all crosstalk capacitance to ground. HiPer PX supports hierarchical and incremental extraction, to model only those cells that have changed since the last extraction. In addition, designers can perform the extraction with different settings at different hierarchy levels, extracting smaller leaf cells, for example, in 3D mode for greater accuracy, while extracting interconnects between them in 2D mode for greater speed. As process sizes drop below .25µm, IC designs with taller, narrower interconnects become more common. While these design techniques save space on the chip, they give way to parasitic capacitance and resistance. Designers must use software tools to model and extract these parasitic effects, or run the risk of chips that function in simulation but fail in silicon and require a re-spin.