According to UMC, it soon plans to offer this new flow to its global roster of customers.
By stacking silicon die or chiplets on top of each other in a single packaged device, companies can achieve the functionality of multiple devices on the same or smaller chip area. This not only saves space but also enables companies to achieve greater system performance and functionality at lower power than traditional configurations of laying out multiple chips on a PCB.
“We are pleased to be able to offer our customers a robust and proven foundry design kit and associate workflow that they can use to validate their stacked device designs, and help correct die alignment and connectivity, while extracting assembly parasitics for use in signal integrity simulations,” said Osbert Cheng, vice president of device technology development and design support at UMC. “Our mutual customers are increasingly interested in 3D IC solutions for applications including high-performance computing, RF, and AIoT, and this collaboration with Siemens can help to accelerate time-to-market of their integrated product designs.”
UMC developed its new hybrid-bonding 3D layout vs. schematic (LVS) verification and parasitic extraction workflow using Siemens’ XPEDITION Substrate Integrator software, together with Siemens’ Calibre 3DSTACK software for inter-die connectivity checking, Calibre nmDRC software, Calibre nmLVS software, and Calibre xACT software for IC and inter-die extended physical and circuit verification tasks.
“Siemens is pleased to continue our collaboration with UMC, which has once again resulted in delivering significant benefits to our mutual customers,” said AJ Incorvaia, senior vice president of Electronic Board Systems at Siemens Digital Industries Software. “As these customers continue to develop higher complexity designs, UMC and Siemens stand ready to deliver the advanced workflows that customers need to help bring these increasingly sophisticated designs to life.”
