When Marcus Yip and Professor Anantha Chandrakasan of MIT presented an A/D converter design for biosensing applications at the 2011 International Solid State Circuits Conference (ISSCC), a key target was flexibility, as the biopotentials used to measure heart and brain signals vary widely in bandwidth and dynamic range. Their approach was to implement the converter using reconfigurable hardware so resolution and speed could be changed ‘on the fly’. Although programmable gain amplifiers on the front-end can help boost effective range, reconfigurability makes it possible to tune power efficiency.
In order to compare efficiencies among converters with different resolutions and sample rates, circuit designers tend to use the metric of energy per conversion step. Less than 100fJ/step is generally a good result for a modern process and novel techniques have seen researchers push this metric down into the low tens.
However, the issue for reconfigurable A/D converters is that, although they can hit equivalent peak efficiencies, their energy per step increases as the circuit moves out of its sweet spot. For example, while the MIT design outlined at the 2011 ISSCC had a peak efficiency of 22fJ/step at 10bit resolution, energy consumption increased to 143fJ/step at 5bit resolution.
A year later, a team from research institute Imec’s Holst Centre described a core that could deliver efficiency across a wider operating range. This applied novel techniques, allowing the accuracy and noise level of the comparator to be tuned to suit the target resolution. The noise for sampling to a 8bit level is allowed to be double that of a 10bit conversion. This slashes energy consumption almost fourfold. Bypass paths made it possible to separate out and shut down the circuitry needed for the most significant bits of a full 10bit conversion.
The main focus in reconfigurable architectures like those developed at MIT and the Holst Centre has been on the venerable successive approximation (SAR) converter. First introduced in 1975, the SAR approach fell out of favour because it lacked the speed of flash and pipelined architectures and could not compete with the resolution of sigma-delta.
SAR converters use a binary-search algorithm to find the digital code that is as close as possible to the analogue input. The algorithm takes as many search steps as there are bits of resolution, which tends to limit its speed at higher resolutions. This leads to a ‘push-pull’ between SAR and sigma-delta architectures in commercial designs.
“Signal bandwidth, together with the latency aspect, tends to determine whether a SAR or sigma-delta architecture is chosen,” says Darren Hobbs, director of product management at IP and design house S3 Group. “For integrated solutions, SARs are now dominating at resolutions of less than 14bit. For greater resolutions, sigma-delta still tends to be chosen.”
In IoT-focused designs, SAR has a further advantage, Hobbs says. “The low latency and fast wake-up time of SAR converters also help with power reduction. If they are not converting continuously, they can easily go to stand-by mode with minimum or zero power consumption, therefore extending battery life.”
To perform the binary search, the SAR uses a D/A converter based on a switchable network of capacitors to generate a reference voltage and, under logic control, updates its output as the voltage moves above and below the captured sample. A comparator guides the internal digital logic on whether the reference voltage should move higher or lower. It is a structure that becomes more efficient than competitors as processes scale down.
Tatsuji Matsuura of the Tokyo University of Science, says the SAR A/D converter is ‘inherently a low-power device because it does not use operational amplifiers’. Op-amps tend to fare badly in highly miniaturised processes because of their need for high gain factors. The intrinsic gain of the transistor drops away as it shrinks and the advanced processes also suffer from voltage reductions.
There are still energy costs to deal with. Hobbs (pictured left) says: “SAR power consumption is directly related to capacitor size. A high linearity requires very small mismatch on the capacitors, which means large devices. But, by introducing calibration techniques, we can correct the mismatch present on small devices digitally. Therefore, we can use small devices, meaning low power, while keeping the high linearity conversion.”
Recent research papers, such as the one presented by the Holst Centre at ISSCC 2015, have focused on other capacitance reductions. This design reduced the figure of merit to 2.4fJ/step on a 65nm process through the use of a bidirectional comparator and attempts to make the capacitors themselves as small as possible. Bidirectional comparisons allow both the charging and discharging phases to be used, almost halving the overall energy of each conversion.
A further change lay in the use of an onchip reference voltage generator that was decoupled from the supply voltage and worked in the subthreshold region. Because the difference between normal and high-threshold transistors within the process was more stable, the design took advantage of that to provide the reference.
The power consumption of the modern SAR will see it pushed further into the domains of sigma-delta and pipelined converters in the directions of resolution and speed, respectively. But the nature of the architecture means it faces limits.
“There is a large body of research ongoing to find solutions to overcome these limits,” Hobbs says. “The trend we see today is not to replace the SAR by something else, but instead to improve the SAR with features or characteristics from other architectures to make it even more flexible and powerful.”
For example, S3 has used hybrids of SAR and pipelined architectures to push sampling rates to 200MHz in commercial circuit designs. The research community has published work on similar hybrids that operate in the gigahertz regime. In general, a pipelined approach coupled with the SAR circuit makes it possible to reduce internal clock speeds. “Achieving higher sampling rates requires time-interleaved cores, which we do as needed,” Hobbs says.
When it comes to higher resolution, SAR is hybridising with the sigma-delta converter. The sigma-delta architecture has always provided scope for trading off resolution against speed through changes to the digital decimation filter that forms the bulk of the converter’s circuitry.
A team from Michigan State University has taken the idea further by building a hybrid architecture that can be tuned to be more like a SAR or a sigma-delta, depending on the required speed and resolution. Where higher speed is more important, the circuit’s SAR characteristics take over.
With power efficiency and implementation cost dominating IoT-focused designs, the SAR looks certain to continue its takeover on a larger scale.
