Processor developers respond to new demands on telecom carriers and content providers

This is forcing telecom carriers and large content providers to rethink how they can maximise their computing, storage and networking resources in this more complex environment. Such requirements explain the growing interest in initiatives such as software defined networking (SDN). SDN optimises how computing, content caching and networking are performed and enhances network flexibility by making the underlying switches and routers appear as virtual resources. At first glance, it is not obvious how such developments impact silicon. But one company looking to benefit is EZchip Semiconductor. It has announced a new class of network processor (npu) that spans the processing requirements for all the higher networking layers of the Open Systems Interconnection model, from layer 2 to layer 7 (see fig 1). The EZchip device will also be C programmable, unlike traditional npus that use assembly language or microcode. Called the NPS, or network processor for smart networks, the device will match the layer 2 and layer 3 packet processing capabilities of leading npus, but will also tackle higher layer tasks such as cyber security, deep packet inspection and load balancing (see fig 1). However, EZchip is not alone in looking to tackle layer 4 to 7 tasks; multicore processors are also available from companies such as Netronome, with its NFP-6xxx. Deep packet inspection enables operators to analyse more closely packet content that can enable them to offer more sophisticated services. Load balancing is used to manage the requirements placed on servers and switches in the data centre to improve efficiencies. The NPS will also support SDN. Because SDN separates the network's control and data planes, the assumption is the data plane becomes simpler. In practice, the opposite is true: the processing become more complex, says Amir Eyal, EZChip's vice president of business development. SDN can segment the network in different ways, independent of the underlying switch and router platforms. This allows multiple customers to use the network, with networking resources assigned or moved from one network to another, regardless of the underlying platform deployment. "That puts more demand on switches and routers – the forwarding nodes – to reconfigure themselves and to handle different packets with different encapsulation schemes, some of which are proprietary," Eyal added. The device must also process data structures such as tables, moving entries between them and keeping the information synchronised. A high performance, yet flexible, device capable of performing these tasks is much desired by equipment vendors, in Eyal's view. The NPS device family is being aimed at traditional telecom applications such as Carrier Ethernet and, in particular, edge router platforms. By also looking at opportunities within the data centre, the NPS will effectively double EZchip's total addressable market. Architecture In order to handle the more complex processing, the packet processing performance of the NPS will be boosted. The NPS-400 will be a 200Gbit/s duplex packet processor, with twice the performance of the NP-5, EZchip's flagship npu. The company has redesigned the basic packet processing unit that forms the basis of the NPS' hierarchical processing array, adding an 32bit ARC risc core. "The NPS abandons the proprietary microcode programming and tools of traditional npus in favour of full C language programming and a familiar Linux debug environment," said Bob Wheeler, senior analyst for networking silicon at the Linley Group. "These changes reduce the learning curve for npu programmers and should improve time to market for complex applications." The elemental processing element within NPS is the CTOP (C programmable task optimised processor). This combines the bit manipulation expertise of EZchip's npus with the ARC core, creating a multithreaded core with a powerful bit manipulation instruction set, programmable in C. "The main architectural change is to a full symmetric multiprocessor design," said Wheeler. "EZchip's NP-5 uses a functional pipeline designed for processing individual IP packets." EZchip has, so far, announced two devices: the NPS-400, with 256 CTOPs; and the NPS-200, with 128 CTOPs. Each CTOP can process 16 instruction threads, whereas the standard ARC core is single threaded. The result is the NPS-400 can process 4096 instruction threads. Also added to the CTOP is a memory management unit for operating system support, while the device's memory bandwidth performance has also been boosted. Groups of 16 CTOPs are combined into what EZchip calls a network processing cluster, which includes a shared level two cache, local memory, hardware accelerators such as a DMA engine and TCAM, and an interface to chip level buses (see fig 2). For the NPS-400, 16 network processing clusters are included, while the NPS-200 has eight. The NPS-400 has an I/O capacity of 800Gbit/s and features EZchip's traffic manager, which controls the scheduling of traffic after it has been processed and classified. For layer 7 tasks such as deep packet inspection, the processor performs several functions, including accessing the packet payload and maintaining states. This latter function is accomplished by tracking the session's progress and looking at subsequent packets that make up the session while remembering the previous state. The NPS must also reorder packets and reassemble payloads of several packets into one block of data, perform pattern matching to see if the content matches one or more entries in the database and take actions such as generating alerts, modify packet contents and/or forwarding the packet to some destination. All these functions can be programmed in software, claims Eyal, and do not require specialised hardware. That said, each network processing cluster includes a deep packet inspection accelerator. While the NPS' power consumption has yet to be detailed, Eyal says it will be comparable to the NP-5, which draws 60W. EZchip says up to eight NPS chips could be put on a line card to achieve a 1.6Tbit packet flow each way, power consumption permitting. Adopting the NPS processor will eliminate the need for platforms to include service line cards with general purpose processors. It is these processors that currently perform the layer 4 to 7 tasks; eliminating the service cards means more NPS based cards can take their place, boosting the platform's overall packet processing performance (see fig 3). The company started designing the NPS two years ago and expects first samples at the end of 2013, with products based on the device expected in 2015. Meanwhile, EZchip says it is sampling its NP-5 npu this quarter. The NPS will overlap with the NP-5 and will be available before the NP-6, the next npu on EZchips roadmap. Given the NPS-400 will have twice the throughput, will that device family affect sales of the NP-5, even when used solely for traditional layer 2 to 3 tasks handled by npus? EZchip says new customers are likely to adopt the NPS, given its support for high level programming. But existing NP-4 customers may prefer to stay with the npu family, due to their investment in software.