Network processor set to support 200Gbit/s throughput

"We don't know of any device, announced at least, that comes close to this [level of throughput]," said Amir Eyal, EZChip's vice president of business development. EZchip says that, by 2014, when equipment using the device will be deployed, four or even eight NP-5s could be integrated on a line card, achieving a total packet throughput of 1.6Tbit/s per board. The NP-5 classifies and routes packets and has an end to end network awareness equivalent to supporting layers 2 to 4 of the Open System Interconnection reference model. "In the NP-5, we provide the ability to reassemble IP packets," said Eyal. "That is typically a Layer 4 function, but requires abilities, like caching of traffic, which are beyond Layer 4." The device's main functions are programmable packet processing and traffic management. Other functional on chip blocks include an integrated Ethernet switch fabric adaptor, media access controllers (MACs) that support 1, 10, 40 and 100Gbit Ethernet and a redesigned memory controller that allows DDR3 only memory to be used to reduce overall system cost. "The reason [the NP-5] is noteworthy is mainly integration, as it reduces a full duplex 100Gbit/s packet processor and traffic manager to a single chip," said Bob Wheeler, senior analyst at The Linley Group, at whose Tech Carrier Conference in June EZchip disclosed its device. "Integration is key as line cards move from 100Gbit/s to 400Gbit/s." The NP-5 processes packets using task optimised processor engines (TOPs). These are common across all of EZchip's processors, including the NPA access network devices (see NE 24 Nov 2009). Four styles of TOP are used. Two perform classification – parsing, which extracts packet headers and data fields, and searching using look up tables; and one TOP each for packet modification and packet forwarding. The TOPs are smaller than a risc core, allowing a large number to be integrated on a die, says EZchip. Each 64bit TOP processes a single thread. A scheduler allocates a packet to the next available TOP. While EZchip does not disclose the number of TOPs per ic, it says the NP-5 will have almost twice as many as the NP-4, with most being used for searching, due to the numerous look ups needed. An on chip ternary content addressable memory (tcam), meanwhile, supports more sophisticated look ups and operates in parallel to the simpler TOPs based searches. As implied, the traffic manager provides bandwidth and guarantees a certain service level to particular packet flows. The traffic manager makes decisions when packet congestion occurs based on a given traffic's priority and its associated rules. For example, a high definition video stream may have highest priority over other traffic types. The device is rated as capable of processing 300million packet/s, each 64byte long. The traffic manager also can operate hierarchically: an application can be given a certain priority and guaranteed bandwidth, while at the next level several applications are aggregated with a certain guaranteed bandwidth. "A customer may have voice, video and data and you want to provide a service level guarantee for the combined services," said Eyal. Here traffic is aggregated from one or more sources and sent to many subscribers. "They need to be managed in larger chunks," said Eyal. The NP-5 first stores packets in its internal buffer memory, dropping lower priority packets once memory is full. It is rare that all input ports are full simultaneously. By taking advantage of the integrated MACs, up to 24 10Gbit ports can be used to input data, so the NP-5 can support peak flows of 240Gbit/s, or a 2.4:1 oversubscription rate. This equates to a system line card supporting 24 ports at 10Gbit/s traffic at the same cost as a 10 port 10Gbit/s design, said Eyal. The NP-5 will have four integrated engines. Each will support either 12 x 10Gbit Ethernet (GbE), 3 x 40GbE, 1 x 100GbE or one Interlaken interface. Two of the four interface engines support 48 1GbE ports using the QSGMII interface, while the remaining two support 12 x 1GbE ports using the SFI interface. While the QSGMII interface interleaves four ports per link, an additional device is needed outside of the NP-5 to deinterleave the data. The SFI interface allows direct connection to a 1GbE optical module. Also included is an Ethernet fabric adapter that supports 24 10Gbit/s short reach backplane interfaces. As for external memory, the device supports up to 24 16bit DDR3 devices. While the NP-4 supports DDR3 and RLDRAM, EZchip decided to base the NP-5 solely on DDR3 to reduce system cost. "RLDRAM costs about five times DDR3," said Wheeler. "By using DDR3, the NP-5 memory cost is about the same as that for the NP-4 at 100Gbit/s." The DDR3 buffers the output packets and stores the packet forwarding and policy look up tables. "Some can be very large, with hundreds of thousands – even millions – of entries per table," said Eyal. The memory also holds statistics such as packet counts, which are forwarded for network management and billing tasks. "Using high latency DDR3 for both look ups and packet buffering at 300m packet/s is extremely challenging," said Wheeler. "The downside of this approach is [that the NP-5 will require] 2401 pins." Synchronous Ethernet and the IEEE1588v2 standards are also supported, used for such applications and mobile backhauling of traffic. The NP-5 will be implemented using TSMC's 28nm cmos process and is expected to consume 50W. Power dissipation is a significant challenge for system vendors. There is an upper limit to the power that can be dissipated within a shelf – and hence a line card – while larger telecom operators have declared they want a 20% reduction in their network power consumption by 2020. EZchip has designed the NP-5 to allow dynamic modification of voltage and clock frequency to save power when the processing load is reduced. It will also power down certain interfaces when not in use as well as certain processing engines. "High end routers have line card power budgets of 300 to 400W, so 50W isn't unreasonable," said Wheeler. "EZchip's use of DDR3 memory also helps reduce power for memories compared with designs that require more tcam or some sram." The NP-5 is scheduled to sample by the end of 2012. Assuming it will take 18 months to design NP-5 based systems, line cards supporting multiple 100Gbit/s interfaces will be deployed from mid 2014. Meanwhile, the NP-4 is expected to be in volume production shortly and EZchip says most large edge router and switch vendors are designing the part into their systems. "They have made a huge investment [in developing existing EZchip processor based systems] and as long as we provide them with a good roadmap then they are likely to continue with us," Eyal concluded.