One of the great challenges to retaining a general purpose computing model in a multicore silicon age is that processors typically execute instructions individually. There may be a capability to execute more in each cycle, but memory delays tend to restrict this and thus questions are raised as to how much performance improvement can be drawn from parallelism alone.
A team from the University of Texas at Austin (UT-A) believes it has come up with a potential solution – a new class of processing architectures known as Explicit Data Graph Execution (EDGE – not to be confused with the enhanced data rate GSM technology).
The TRIPS (Tera-op, Reliable, Intelligently adaptive Processing System) project has been under way for five years, but prototype silicon was only released in April this year.
