TRIPS into the future

TRIPS (the Tera-op, Reliable, Intelligently adaptive Processing System) is based on an explicit data graph execution (EDGE) architecture and has three main components: the chip itself; the instruction set; and the compiler. The nature of that compiler is critical to how the chip boosts multicore performance. It works from an assumption of no radical short to medium term change in software development models. “We also looked ahead 10 years and assumed that wire delays are going to be pervasive,” explained UT-A Professor Kathryn McKinley. “We then asked ‘What if we expose those wire delays to the compiler so that it reasons both for latency and also what can be achieved in parallelism at a very fine grain?’. By changing the ISA, we have exposed the parallelism to the compiler and now it can reason explicitly that two instructions are independent, schedule them on separate processors and then, to minimise latency, address subsequent instructions to very closely colocate them with others with which they communicate. “With risc,” she continued, “they find those dependencies for each instruction by looking them up against a big shared structure. Our compiler communicates at a very fine grain level that handles the process more efficiently.”