Excited about emulation: Interview with Mentor's emulation specialist Eric Selosse

Emulation was once the preserve of the 'big boys'; those companies with cash to spare and, more importantly, large designs to test. Smaller companies, or those without a suitably large budget, had to use other means to determine whether their chips were bug free. "But the world has changed a lot in the last four or five years," claimed Eric Selosse, general manager of Mentor Graphics' emulation division. "Emulation technology today is not far removed from supercomputers." Because emulation was a technology with a limited customer base, it sat on the side; developers didn't want to make the necessary investment because they didn't see an obvious return. "But the technology started to work for more companies," Selosse continued. "We have been able to make emulation a tool which more people can use and, as a result, customers are coming back." But while demand for emulation is growing, so too are the requirements they are placing on those developing emulation systems. "Customers want more emulation capability," Selosse conceded, "but they don't always want the price to rise." What has enabled Mentor to meet these needs is a custom ASIC. "Because we design our own ASICs, systems and software," Selosse continued, "we can provide more capacity from smaller machines and that allows larger designs to run. The base technology is similar to an FPGA, but there is also multiplexing technology to make the array work better." An array of chips can be interconnected and a design partitioned across them. Selosse noted the use of an active interconnect technology that is 'not so far removed from networking router technology'. "It provides for a constant delay between any two chips in the system," he said. The emulation system is built using boards with 16 ASICs each and the top of the range devices are capable of handling 2bn gate designs in one go. Mentor is also taking advantage of process technology and its ASICs are currently designed for a 28nm process. "But we're now looking at FinFETs to see what benefits that could bring," he added. What is driving demand for emulation is the rapid increase in the size of chip designs – Selosse talks about billion gate devices – as well as the rate of change in these designs. "Because older emulators were much slower, there was always an older version of the design being verified. We modified the compiler flow in our emulators a few years ago and this has changed the world; the tool can now be used every day. The emulator uses the latest design data and this changes the way in which emulation is viewed. Now, it's a mainstream design tool; it's faster and it's cheaper. Emulation would have remained a side show unless we enabled big designs to run in a matter of hours; machines that couldn't cope with the pace of design changes." A side effect of design size is the need to partition. "Engineers were emulating specific parts of the design in the past," he continued. "They would say 'OK, we had an issue with this area, so let's verify it on the emulator'. Now, there's a lot more design reuse than five years ago, but design reuse doesn't mean the IP will be bug free; emulators are helping to perform long regression tests. When you run a very long set of tests, it gives the security that everything is working." He also pointed out that customers are moving to using verification earlier in the design process. "What used to be verified post silicon is now verified pre silicon. If it doesn't boot, it doesn't get taped out." Because emulation still represents a major investment, customers want to make the most of it. "We're looking to make emulation more useable," Selosse said. "We want to make it more of a 24/7 technology which doesn't need so many people to run it and to create a system which could be started or stopped remotely." Another facet of emulation technology is the move to bring multiuser abilities. "If they buy a system with 64 boards," Selosse said, "they want access to all of them, so we've had to create new technology that allows them to 'split' the box; it's much like queuing in mainframes. The system assesses the priorities and finds boards or chips that aren't being used. This means designs can run in parallel and the system can also be run in batch mode." With this 'supercomputer like' performance, will emulators find application in other industries? "Yes," Selosse said. "We have a few experiments running. Although we have yet to prove this idea, we think a basic model of a chip loaded in the emulator could verify a large amount of what ATE systems do. "We're anticipating entering new industries, so we've created OS3, which can produce an interface layer that connects apps; there won't be the need to redevelop the hardware." He also sees potential applications in software development. "Take an embedded processor, for example. The emulator could have a tool which allows you to run the software and do fast forwards and rewinds. If you have to run through 2million cycles, you don't want to use normal speed; rather, you want to fast forward to where you need to be. The idea is to run software on the processor model and to know at the end of the test that you have a bug." Emulation is now benefiting from a growing customer base. "Emulator developers are more willing to invest in the technology because they can see a return on that investment," Selosse concluded. "The market is growing and that's generating interest and investment." Eric Selosse Eric Selosse joined Mentor Graphics in 2000 from Bull's Open Systems division. He was recently promoted from general manager of Mentor's Meta Systems division to his current role as vice president and general manager of its emulation division and has global responsibility for Mentor's emulation products. With an engineering degree in electronics, Selosse has also held engineering and marketing positions with IBM's networking division in the US and France.