Advances in regularity for SYNAPTIC project

Supported by the European Union's Seventh Framework Programme, the SYNAPTIC research project includes eight partner organisations from across Europe who have joined forces to develop new microprocessor design methods and related EDA tools. At the heart of the project is the development of regularity aware synthesis methodologies, first at the architectural level, then at the synthesis level, and finally in layout generation and integration of the new methods into EDA tools. Amongst the consortium partners are STMicroelectronics, Thales, imec, Nangate and Leading Edge, which is participating as a consultancy company specialising in the introduction of innovative EDA technologies to the European marketplace. According to Martin Elhøj, SYNAPTIC Project Coordinator with Nangate, the consortium examined regular structures in computing architectures and engines, which led to the selection of two industrial test benches that will be used by the project to evaluate the benefits of new synthesis and layout generation algorithms and methods. Work is progressing with the development of tools and methodologies that extract regularity at the structural level and use these results to drive the optimised generation of application specific custom Boolean functions. This approach will overcome the limitations of traditional synthesis methods that rely on a standard library alone. An innovative layout generation flow was established that is said to enable the automatic generation of standard cell layouts with configurable levels of regularity. Based on this flow, the consortium has developed two cell architectures that take lithography effects into consideration and thus enhance manufacturability and aim at reducing variability. The two architectures are Via-Configurable Transistor Array (VCTA), an extremely regular fabric, and (2) ALARC (Adaptive Lithography Aware Regular Cell), a more conventional regular cell with design restrictions imposed by lithography limitations. 'Significant improvements' in the netlist synthesis step have also been achieved, leading to reduced transistor count and thus improved cell area. The benefits of the regular design methodology will be evaluated at several levels, including lithography evaluation for both logic and sram. In particular, a litho process variability aware methodology to characterise sram variability was defined. An integral part of the project is the exploitation of the developed methods and algorithms in commercial EDA tools and to ensure that the methodology can be integrated into commercial design flows. Significant progress has been made by the integration of the innovative regular layout generation flow into a SYNAPTIC variant of the Nangate Library Creator™. Nangate anticipates that the methods developed in the project's first year can be exploited in its commercial tools in the very near term.