Microelectronics project to enhance lithography based yield

The partners say that, with the introduction of advanced process nodes, significant layout restrictions lead to a more regular layout style being applied for the fundamental logic cells. But they add that, to enable technology scaling to remain attractive, it is necessary to counter the negative effects of regularity restrictions on logic density. It is therefore critically important to focus research efforts on exploring and developing innovative design techniques and methodologies, along with associated CAD tools and logic cell libraries, which remove the limitations in design implementation effectiveness associated with technology scaling and advanced sub wavelength lithography. From an architectural point of view, the partners are looking to exploit step and repeat approaches employing complex logic cells and complex logic building blocks, providing greater predictability of design performance and enabling early architecture exploration. From a logic design point of view, advantages include the creation of logic cell libraries targeted to design requirements, thus improving performance and performance predictability. From a physical design point of view, this project is looking to enable the use of lower cost lithography techniques while achieving the same yield. The consortium partners are STMicroelectronics, Thales, Imec, Politecnico di Milano, Universitat Politècnica de Catalunya, Universidade Federal do Rio Grande do Sul and Leading Edge. Work will be coordinated by Danish company Nangate.