This is the first RISC-V CPU IP certified to be fully compliant with ISO 26262 functional safety standards.
SGS-TÜV Saar, an independent functional safety certification body, has assessed and completed product audit process for N25F-SE with achieved functional safety for ASIL B (Automotive Safety Integrity Level B) applications, according to all applicable ISO 26262 series of standards including Parts 2, 4, 5, 8 and 9.
The N25F-SE is a 32-bit RISC-V CPU core that supports standard IMACFD extensions, including efficient integer instructions and single/double precision floating point instructions. It incorporates the Andes V5 extension instructions to further boost performance and reduce code size.
The 5-stage pipeline of the N25F-SE provides high operating frequency along with a compact design. Flexible interfaces simplify SoC designs and comes with rich configurable options, all of which are fully certified, which means that SoC design teams are not limited by one fixed CPU configuration when offering automotive solutions.
ISO 26262 defines functional safety as the “absence of unreasonable risk due to hazards caused by malfunctioning behaviour of electrical/electronic systems”. To enforce functional safety with a reasonable cost structure, proper safety measures for desired ASIL levels should be applied, from the least stringent ASIL A to the most stringent ASIL D.
Examples of electronic systems where ASIL B is sufficient are dashboard, in-car monitoring, keyless entry, lighting control, tire pressure monitoring, vision ADAS, and window control.
Either to incorporate new electronic systems on board, or to upgrade existing ones without ISO 26262 compliance, the N25F-SE has been developed for a broad range of applications requiring ASIL B compliance.
“Andes is the first RISC-V CPU vendor certified, for the development process of automotive processor cores, to be compliant with ISO 26262 standards up to ASIL D in 2020. With the certified development process in place, we formally started our functional safety roadmap to deliver at least one ISO 26262 compliant core every year to cover all segments of performance and features,” said Dr. Charlie Su, President and CTO of Andes Technology. “Andes has developed a wide range of AndesCore processors, from driving cost sensitive MCUs to accelerating datacentre AI/ML computations. We are pleased to announce our first safety-enhanced AndesCore the N25F-SE based on the most popular and mature CPU IP family, the 25-series.”
The ASIL B fully compliant N25F-SE was developed under considerations on all applicable requirements of ISO 26262 standards by defining tailored safety activities.
It comes with the Safety Package which includes Safety manual, Safety analysis report (FMEDA and more), and Development Interface Outline. Together, the N25F-SE and its Safety Package offer an efficient and flexible automotive solution that will greatly reduce the time for SoC design teams to certify their ISO 26262 compliant SoCs.
In addition, the N25F-SE helps reduce the cost and power consumption for SoCs requiring only an ASIL B processor IP without forcing them to use a double-sized dual-core lock-step solution with ASIL D.
“As the only public RISC-V CPU IP company and a leader in the RISC-V ecosystem, we want to raise the awareness of the importance of ISO 26262 full compliance,” added Dr. Su.
