This IP is designed to meet FPGA timing limitations to run at slower frequencies at less than 200 Mhz while still providing the necessary bandwidth.
Arasan’s MIPI DSI IP for FPGA has been seamlessly integrated and tested with its MIPI C-PHY / D-PHY Combo ASIC. The C-PHY / D-PHY ASIC is available on a FPGA HDK configured with MIPI DSI Tx and Rx or CSI Tx and Rx from our partner Testmetrix.
The target market for this FPGA version is production test and compliance test companies who currently use or are adopting Arasan’s CSI and DSI IP or companies looking to have a C-PHY based FPGA solution for prototyping or limited production using Arasan’s C/D-PHY Combo ASIC.
Arasan also licenses its C-PHY / D-PHY Combo IP on foundry nodes down to 5 nm for companies to migrate or implement on an ASIC.
Arasan also offers VESA DSC Encoder and Decoder IP as part of its Total MIPI Display IP Solution.
The MIPI DSI IP for FPGA is available for immediate licensing.
