ARM unveils interface spec for its v8 processor architecture

William Orme, strategic marketing manager, said the specification was aimed at the enterprise and networking sectors, where many processors are connected to provide the necessary performance. "We have developed 5CHI to for greater frequency interconnect and for more scalability." Orme said 5CHI takes AMBA 4 ACE technology to the next level of scalability. "The key advantage," he said, "is that it allows interconnect designers to choose how they trade off performance against cost, in terms of power consumption and silicon area." AMBA 5 CHI has been developed by ARM in association with its semiconductor partners, third party IP providers and the eda industry. The protocol already features in the ARMv8 based Cortex-A57 and Cortex-A53 processors and the CoreLink DMC-520 Dynamic Memory Controller. It is also used by the CoreLink CCN-504 Cache Coherent Network, which supports data rates of up to 1Tbit/s. Orme said 5CHI supports more masters in a network and introduces the concept of an L3 cache distributed around the interconnect. "New features include a non blocking structure that ensures all information will always flow freely around the network."