The company has introduced new features in its QEMU software virtual machine emulator based Linux host and SoC RTL co-simulation solution for system-level verification of complete CXL HW-SW systems.
Avery said that it was looking to push the leading edge of CXL adoption with new enhancements specifically aimed at enabling pre-silicon validation of the upcoming 3.0 version of the standard, which will double bandwidth with the same latency as previous versions.
The most recent enhancements expand the capabilities of its QEMU-CXL platform and include the Latest linux kernel 6.0.1 supporting CXL and interoperability tests such as using cxl-cli for memory pooling provisioning, resets and Sx states, and Google stressapptest using randomised traffic from processor to HDM creating realistic high workload situations.
The entire platform supports pre-silicon design of SoCs leveraging version 3.0 and prior 2.0/1.1 versions of the CXL standards.
Co-simulating the SoC RTL with a QEMU open software virtual machine emulator environment allows software engineers to natively develop and build custom firmware, drivers, and applications and run them unaltered as part of a comprehensive system-level validation process using the actual SoC RTL hardware design.
Hardware engineers can now evaluate how the SoC performs through executing UEFI and OS boot and custom driver initialisation sequences in addition to running real application workloads and utilize the CXL protocol aware debugging features of the VIP to effectively investigate any hardware related issues.
“Combined with our CXL compliant VIP, our QEMU CXL virtual platform and VIP co-simulation enables complete CXL system-level bring-up of SoCs in a Linux environment. With this approach customers can address new CXL 3.0 design and verification challenges even when no mainstream commercial platforms support the latest standards,” explained Chris Browy, vice president sales/marketing at Avery.
