Unveiled at the IEEE International Solid-State Circuits Conference, imec’s massively time-interleaved slope-ADC design provides a combination of high-power efficiency and a very compact footprint, while promising to enable exceptional fast conversion speeds.
It is intended for data centres that are experiencing an explosion in data processing and throughput demands, driven by the surge in cloud computing and (generative) AI applications.
Training AI models requires massive computing power, requiring data centres to invest in increasingly powerful optical networks for fast, reliable communications between servers, storage devices, and networking equipment. However, since data centres' optical communication networks need to operate at higher and higher speeds, their components have been growing in size and power consumption.
A critical component of optical transceivers, wireline ADCs are mostly based on time interleaving of (large numbers of) successive approximation register (SAR) ADCs that feature tens of parallel high-speed channels. As such, when scaling to sampling rates far beyond 100GS/s, the SAR ADC approach results in a significant area increase and long interconnection lines, translating into substantial parasitics and energy loss.
In response, imec has proposed a new ADC architecture that overcomes these limitations.
“On the one hand, our massively time-interleaved slope-ADC design exploits the paradigm that slow-speed, but extremely small channels make for a more efficient conversion per area. Secondly, by arranging (lots of) these channels in a two-dimensional array, the length of the interconnection lines is minimised, and the power dissipated through parasitics is reduced.
“As a result, higher power efficiency and scalability can be achieved, while significantly reducing the ADC’s surface area,” said Joris Van Driessche, program manager at imec.
At ISSCC, imec presented a proof-of-concept of its new ADC architecture in the form of a 42GS/s 7b massively time-interleaved slope-ADC prototype chip.
“Implemented in 16nm FinFET technology, our prototype chip contains an array of 768 slope-ADCs – with a core active area of just 0.07mm². This is at least a factor of two smaller than conventional approaches. It also has a state-of-the-art power consumption of 96mW,” explained Joris Van Driessche. “In other words, this is the first proof that our novel architecture works. And its benefits will only become more significant as we move to higher speeds (150GS/s and beyond).”
In fact, a 5nm ADC using the same architecture is currently being completed – targeting sampling rates well above 150GS/s while achieving extremely low power consumption. In parallel, the team has started exploring a 2nm implementation, targeting speeds in excess of 250GS/s.
“We believe this is an important stepping stone in the development of a whole new generation of small-area, low-power ADCs to support tomorrow’s wireline applications. It overcomes the limitations of SAR ADC implementations, which risk running out of steam when required to operate at extremely high speeds,” concluded Van Driessche.
Imec is encouraging additional partners to join this research effort – such as fabless companies specialising in the development of wireline connectivity building blocks. Moreover, licensing options are available for those companies seeking access to imec’s ADC IP blocks.
