‘Breakthrough’ technology cuts phase noise by 90%

The electronics giant claims the breakthrough will pave the way for a further migration to high speed wireless communication chips for wireless LAN and WiMAX. The time to digital converter is designed to reduce susceptibility variations in mass production and address the need for more robust manufacturability. It integrates interpolation circuits that use a low resistance conductor to connect the output of two inverters. A triple interpolation splits the cycle of output signal of frequency synthesisers and, according to Toshiba, reduces phase noise by 90%. The solution features a stable waveform from the PLL itself as a reference time interval for converting time to digital data, not the delay time of the inverters. In a test chip manufactured with 65nm cmos process, Toshiba claims phase noise was reduced to -104dBc/Hz, 90% lower than that of the previous all digital PLL that the company announced in 2011. Chip size was cut to 0.18 mm2, approximately 80% smaller than the analogue PLL in a mobile WiMAX transceiver chip announced in 2010.