This digital PLL could be an attractive building block for Bluetooth Low Energy (BLE) and other wireless technologies to support a wide range of Internet of Things (IoT) applications.
As a key building block of wireless communication systems, frequency synthesisers need to satisfy demanding requirements. Although analog PLL frequency synthesisers have been the standard for many years, engineers in the IoT industry are increasingly turning their attention to so-called digital PLLs (DPLLs) to achieve ultra-low power operation.
Kenichi Okada, associate professor at Tokyo Institute of Technology's Department of Electrical and Electronic Engineering and his group now report a fractional-N DPLL. This is an emerging class of digital PLLs that are of much interest as they can help improve phase noise. According to the team, this new DPLL achieves a power consumption of only 265 microwatts (μW) - less than half the lowest power consumption achieved to date (980 μW) (see table 1), according to to the Tokyo Institute.
The researchers found that overall power consumption could be greatly reduced by using an automatic feedback control system. "This automatic-switching feedback path consumes a power of 68 μW, which leads to a power consumption of 265 μW for the whole DPLL," assoc prof Okada says.
The promising DPLL could go on to be used as a component for processors, memories and a vast new range of IoT devices that will be expected to be both cost-effective and eco-friendly by running on ultra-low power. Assoc prof Okada notes that early experiments show the DPLL could extend battery life by four times.
