These designs are at the heart of advanced applications such as hyperscale computing, graphics and machine learning (ML) applications and, given the enormous size of these designs, engineering teams are constantly challenged to meet schedule and compute budget.
Through this collaboration, common customers will be able to accelerate their signoff schedule and reduce compute cost by adopting the Cadence Tempus Timing Signoff Solution and TSMC technologies using the ready-to-use Cadence CloudBurst Platform and Microsoft Azure Cloud.
“Semiconductor designers are consistently pushing the boundaries to create increasingly large designs, and it’s critical for design teams to meet their tight product schedules,” explained Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “Over the past year, our close collaboration with Cadence and Microsoft through the TSMC OIP Cloud Alliance has given our customers access to advanced technologies, Cadence signoff solutions and cloud portfolio as well as Microsoft’s Azure platform to seamlessly handle giga-scale designs and quickly launch their differentiated products to market.”
Mujtaba Hamid, general manager, Silicon, Modeling & Simulation at Microsoft Azure added, “Microsoft’s Azure Cloud platform is enabling HPC customers to push the limits on what is possible for demanding scenarios like silicon design signoff. Our collaboration with Cadence and TSMC continues to pave the path for accelerating silicon design through the cloud, enabling the industry to deliver the highest quality products and achieve time-to-market goals.”
To address signoff of giga-scale designs, the Cadence Tempus Timing Signoff Solution features a massively parallel architecture, known as distributed static timing analysis (DSTA).
DSTA is production-proven in the cloud on large-scale TSMC advanced-node tape-outs and provides the scalability deemed necessary to signoff the world’s largest designs. Using DSTA, Cadence was able to demonstrate a methodology that minimised compute cost and completed timing signoff for a 10+ billion transistor design in hours versus days when compared with a traditional non-distributed STA approach.
For customers who want to focus on design excellence and PPA gains rather than expending effort on IT setup and securing a cloud environment, the Cadence CloudBurst platform is able to provide a ready-to-use, EDA-optimised and secure cloud environment for a full design flow or peak demand requirements for specific functions such as timing signoff.
“Through our continued collaboration with TSMC and Microsoft, we’re setting new industry benchmarks and improving customers’ ability to meet their schedules by adopting the Tempus Timing Signoff Solution in the cloud,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “The scalability of our software on the cloud and our ready-to-use Cadence CloudBurst environment enables our customers to efficiently manage the most time-sensitive and demanding semiconductor design projects.”
A white paper that details the collaboration can be downloaded by using the link at the bottom of this page.
The white paper contains cloud scaling strategies focused on distributed execution, detailed illustrations of the Cadence Tempus Timing Signoff Solution cloud execution, sample scripts, Cadence CloudBurst reference architecture and Microsoft’s Azure Cloud IT best practices.
