The adoption of AI applications has created growing demand for advanced silicon solutions that are capable of handling colossal datasets and computations and, to meet these requirements, the broader industry is pushing the boundaries of advanced-node silicon and 3D-IC technologies.
TSMC has certified Cadence’s industry-leading digital and custom design flows for implementation and signoff on its latest N3 and N2P process technologies. As long-standing design technology co-optimisation (DTCO) partners, both companies are collaborating to optimise power, performance and area (PPA) on A16, adding EDA features to enable advanced features such as backside routing.
Cadence and TSMC are also collaborating on Cadence.AI to drive next-generation digital and analogue design automation that’s fuelled by AI, delivering improved productivity and quality of results. Cadence.AI is a chips-to-systems AI platform that spans all aspects of design and verification.
The collaboration between TSMC and Cadence is focused on three main domains:
- The Cadence Cerebrus Intelligent Chip Explorer applies AI to digital design for converging on the optimal PPA.
- The Cadence Joint Enterprise Data and AI (JedAI) Platform uses generative AI for design debug and analytics, helping with PPA analysis.
- Cadence’s Virtuoso Studio enables migrating legacy custom and analogue designs to modern nodes and performs circuit optimisation and high-sigma Monte Carlo analysis.
Cadence’s Integrity 3D-IC Platform is a system-level exploration solution and a single-vendor platform that brings together packaging, analogue and digital implementation - making efficient 3D-IC design possible.
It also opens up new opportunities for innovation by supporting all the latest 3Dblox features and constructs. To enable the ultra-high-density interconnect in TSMC 3DFabric technologies, TSMC and Cadence are working together on a next-generation high-capacity substrate router for die-to-die and die-to-substrate connections.
TSMC and Cadence are also looking to enable warpage/stress analysis for TSMC 3DFabric in addition to electrical/thermal analysis, and Cadence’s Celsius Studio warpage/stress analysis simulation results have been validated.
Thermal and voltage impacts on power/IR/STA are also enabled and verified inside the Cadence Integrity 3D-IC Platform for TSMC 3DFabric.
Cadence has developed a broad portfolio of critical IP for efficiently moving data between chiplets and across data centres, including Universal Chiplet Interconnect Express (UCIe) 1.0, PCI Express (PCIe) 6.0 and GDDR7 on TSMC N3, running at 32Gbps, which is said to provide the best price/performance for AI interfaces in both data centres and network edges.
To address the growing communication challenges between these chips, Cadence silicon photonics design enablement solutions can support TSMC’s Compact Universal Photonic Engine (COUPE).
TSMC and Cadence are also jointly collaborating with companies in the automotive space. As the silicon content in today’s automotive designs continues to grow, IP development for current and future process nodes, such as TSMC N5A and later N3A, is even more critical.
TSMC and Cadence have also collaborated to demonstrate the accuracy and scalability offered by Cadence’s front-to-backend chip design flows on the Cloud for TSMC’s advanced process nodes. Through this collaboration, customers can shorten design schedules by adopting Cadence’s wide range of Cloud solutions.
According to Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence, “We are revolutioniSing the future of silicon design with AI-powered EDA software, enabled for TSMC’s latest process technologies. Our ongoing collaboration on innovative solutions for next-generation technologies like TSMC A16 and 3Dblox is paving the way for the AI factories of tomorrow.”
“In collaboration with Cadence, we’ve successfully enabled AI-optimized design flows for TSMC’s N2 technology and are driving advancements in 3D-IC design,” said Dan Kochpatcharin, head of Ecosystem and Alliance Management Division at TSMC. “This marks a significant leap forward in digital and custom solutions, paving the way for the technology innovations that will power the AI infrastructure.”
