The physical verification flow has been optimised to enable customers using Samsung Foundry’s advanced nodes to reach signoff accuracy and runtime goals in a variety of market areas, including the mobile and hyperscale markets.
Samsung Foundry also delivered an enhanced, signoff-accurate process design kit (PDK) to facilitate the adoption of the Pegasus Verification System on the Samsung 5nm and 7nm technologies.
Pegasus provides massive scalability, which in turn leads to faster turnaround times and more predictable design cycle times with design rule checks (DRCs), layout versus schematic (LVS), hierarchical metal fill (HMF) insertion and design-for-manufacturing (DFM) signoff.
It has been validated with the Cadence Innovus Implementation System, providing improved productivity with signoff-level checks through implementation. Designers will be able to fulfill mandatory DFM signoff requirements by leveraging integrated hotspot detection with seamless automated fixing. Additionally, the Pegasus Verification System features a tight, interactive integration with the Cadence Virtuoso® Layout Suite environment.
“The Pegasus system was architected from the ground up to accelerate the signoff physical verification flow through its massively parallel capabilities and integration into our Virtuoso environment and Innovus Implementation System,” said Michael Jackson, corporate vice president, R&D in the Digital & Signoff Group at Cadence. “This allows our customers to define and meet design schedules with greater predictability.”
