Addressing this annual gathering of developers and engineers, Tom Beckley, general manager of Cadence’s Custom IC and PCB Group, warned the design community was experiencing a ‘new age’ in which ‘innovative physical, mechanical and electrical engineering were combining with rapid developments in software, to deliver an ever smarter world of connected devices’. While many assumed ‘we’re good at both verification and safety’, he suggested that would be a profound mistake. “We are faced with a massive digital revolution and it’s becoming a trickier test world for engineers. As we layer in more complexity, systems are becoming more vulnerable. Everything connected can be hacked.”
According to Beckley: “As complexity grows, so validation and verification need to start earlier in the design cycle if we want to avoid unnecessary and expensive re-runs. We are witness to a massive explosion in hardware and software complexity and, as engineers, we are obliged to make sure we advance technology, but do so safely.”
Complexity is affecting all aspects of product design and Cadence used CDNLive to announce one of its biggest launches in recent years, with new versions of its Allegro and OrCAD platforms.
According to Heman Shah, product management group director for Cadence’s Enterprise PCB products: “Allegro 17.2 looks to significantly reduce the design cycle for PCBs, shortening routing times and ensuring that critical high speed signal performance criteria are met. By simplifying the design process, we want to boost productivity significantly.”
Allegro 17.2 features a comprehensive in-design inter layer checking technology that is intended to reduce the number of redesign iterations and, with the introduction of a concurrent team design capability, is now able to accelerate product creation time by up to 50%, according to Shah.
This latest version of Allegro also provides a number of new capabilities, including: Rigid-Flex design enhancements, that give designers the ability to specify multiple rigid and flex stack-ups in the same database; as well as the ability to create separate material inlay regions, which means that PCBs can now combine expensive and inexpensive materials.
“Material inlay zoning means that we can use less high speed material and cut raw material costs by as much as 25%,” Shah explained.
Cadence also unveiled OrCAD 17.2. “This release comes with a range of new capabilities for OrCAD Capture, PSpice Designer and PCB Designer that look to address challenges with flex and rigid-flex designs, as well as mixed-signal simulation complexities when it comes to IoT, wearables and wireless mobile devices,” explained Kishore Karnane, director of product management for the OrCAD family.
“We are looking to reduce PCB development time with this new version and have focused on the need to design for more reliable circuits in smaller, more compact devices that need to get to market quickly.”
The OrCAD portfolio includes technology enabled for integrated rigid-flex planning, design and real-time visualisation, as well as built-in translators that will enable designs to be imported directly from a number of EDA products.
“In a bid to enable a faster and more efficient flex and rigid-flex design creation, the OrCAD portfolio now uses a new multi-stack-up database capability and extensive in-design inter-layer checks, which will help engineers to avoid errors introduced through manual checking,” Karnane concluded.
