“The design community is calling on companies like Cadence to deliver new tools and technologies,” Beckley said, and while he provided a detailed overview of the company’s product portfolio, he hinted at possible developments, including bringing together Virtuoso, Allegro and Sigrity in a move that would enable design engineers to ‘pull in package and board parasitics while the chip was still open’. “Today, it is not just about the chip, it’s about the product,” he said.
Beckley also talked about the end of Moore’s Law, suggesting that ‘we’re at 7nm, soon 5nm, we’ll go to 3, probably 2, maybe 1. “But that will be it. We’re going to have to start looking at 3D and wafer-level packaging.”
Another issue confronting industry is the demand to bring products to market quicker. “We’re faced with development cycles that are much shorter and engineers needing to deliver smaller, lower power, cheaper, more reliable and, crucially, more highly integrated designs,” Beckley suggested.
To that end, Beckley announced that Cadence was expanding its partnership with MathWorks through a new integration between its Virtuoso Analog Design Environment (ADE) Product Suite and MATLAB.
Working with MathWorks, Beckley described what will be a much tighter integration between ADE and MATLAB.
“Using MATLAB’s toolboxes and language, designers will be able to create and solve complex calculations that would have previously taken them hours using expert coding knowledge and low-level APIs. This data analysis can now be performed in either tool, or split between the two,” explained Steve Lewis, product marketing director for Cadence’s Custom IC and PCB Group.
“It will enable customers to process large data sets much faster when verifying custom, RF and mixed signal designs,” he explained, “and this integration will enable designers to take advantage of existing MATLAB scripts and share data easily between the Virtuoso and MATLAB platforms, allowing efficient analysis in either platform.”
According to Lewis, this improved connection will help to reduce time to market significantly when compared with traditional methods.
“Designs are becoming more complex and analysing the large amount of simulation data being created during the design and verification process is becoming harder,” said Beckley. “By integrating MATLAB with our entire ADE product suite, we’ve cut the time engineers spend analysing their results significantly.
“For customers, this integration simplifies the exchange of data and will boost analytics capabilities. When taken with our previous announcement, regarding PSpice and MATLAB integration, this move has expanded our System Design Enablement offering,” he concluded.
Continuing this theme of greater integration, the second key announcement at this year’s event involved Cadence’s JasperGold Formal Verification Platform and the addition of two new Apps.
“The JasperGold Superlint and Clock Domain Crossing (CDC) Apps are advanced formal-based technologies that address register-transfer level (RTL) signoff requirements,” said Pete Hardee, pictured, director of product management for JasperGold, System and Verification Group.
With these Apps, Cadence is bringing the formal JasperGold technology to the RTL designer’s desktop and, according to Hardee, this will help to improve IP design quality by reducing late-stage RTL changes; in some cases, by as much as 80%. “As a result, IP development time could be reduced by up to four weeks.”
With today’s larger, more complex designs, there is also a growing need to develop robust IP that can then be reused in multiple SoCs to improve productivity. Signoff checks previously performed at the netlist implementation stage now need to be performed on the RTL design.
According to Hardee, traditional static lint and CDC tools have not been effective at ensuring that the RTL code is of the highest quality. However, the latest JasperGold formal-based RTL signoff technologies mean designers will have access to richer functional checks and formal-powered intelligent debugging to reduce violation noise.
“Violation noise is one of the most pressing RTL signoff challenges today,” Hardee asserted.
Superlint and CDC Apps are integrated with the JasperGold Visualize debug environment and use proven formal intelligence to increase debug efficiency for RTL designs.
“Both apps incorporate Cadence’s existing formal capabilities to improve waiver handling. Designers can now perform signoff with robust, reusable and CDC-clean RTL code in the verification and implementation phase, shortening overall time to market and significantly improving design quality,” Hardee concluded.
