CEA-Leti announces breakthrough in innovative multibeam tool
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CEA-Leti says it has made 'significant progress' on the capabilities of the massively parallel direct write technology developed by Netherlands based MAPPER lithography specialist, Delft.
According to the French research and technology institute, it has achieved this in the following resolutions: 22nm dense lines and spaces and 22nm dense contact holes in positive chemically amplified resist. This resolution also meets the industry requirement for the next generation 14nm and 10nm logic technology nodes.
CEA-Leti and Mapper have also announced a three year extension of their Imagine programme – a project to evaluate a maskless lithography infrastructure and use Mapper lithography tools for high throughput. CEA-Leti plans to install one of Mapper's first pre-production Matrix systems, enabling industry to assess maskless lithography technology in a real manufacturing environment. The multi-partner Imagine programme includes TSMC and STMicroelectronics, along with more than 50 representatives from 13 different companies.
Laurent Pain, coordinator of the programme and manager of the CEA-Leti lithography laboratory, said the company's partners were crucial in enabling the state of the art demonstration. He noted: "It demonstrates the capability of this technology that represents a real alternative for advanced semiconductor manufacturing. The outcomes of Imagine reflect the involvement of CEA-Leti to push and promote this very promising lithography solution. We are already preparing the future together with Mapper with the arrival of the first pre-production tool in our premise. By continuing the Imagine programme for another three years, we will continue to answer the increasing interest showed by industry."
Mapper's ceo, Bert Jan Kampherbeek, added: "This breakthrough marks another important step towards the introduction of our innovative tool for semiconductor manufacturing. In 2012, Mapper will complete its Matrix pre-production platform with – initially – a wafer per hour throughput capability and scalable to 10 wafers per hour."