It is hoped that this work will dramatically accelerate the growth of the Quantum Computing (QC) industry by reducing the constrains associated with interconnects and enabling efficient qubit/system scaling.
The architecture of Quantum Computers combined with specialist algorithms have the power to transform computing efficiency to address problems in disciplines spanning fundamental science, pharmaceuticals, finance, logistics and AI.
Most quantum computing platforms utilise qubits or components that operate at cryogenic temperatures but with these platforms there's a lack of suitable control circuitry capable of operating at the cryogenic temperatures needed to manage qubits operation. Currently the control circuitry is located remotely from the qubits and connected by expensive and bulky cabling in order to avoid the temperature extremes needed by the qubits. The amount of cabling required for all the qubits presents a fundamental barrier to QC scaling.
One obvious solution is to co-locate the control electronics with the qubits in the cryostat but this means that both must be kept at ultra-low temperatures; in some implementations down to near absolute zero. However, not only is space extremely limited in the cryostat, necessitating the miniaturisation of the control circuity, but the modern semiconductors that make up these chips are only qualified to work down to -40° C and at those temperatures the operating characteristics of the transistors change markedly.
The aim of this project is to essentially understand and model this change in behaviour and then design a portfolio of CryoCMOS IP to enable the creation of custom chips that can interface to the qubits at cryogenic temperatures and support controller functionality.
Many companies, especially smaller and start-up companies based here in the UK would benefit enormously if a suite of CryoCMOS IP was available to license in much the same way as standard semiconductor IP licensing models work.
The consortium consists of the complete ecosystem of companies to provide the core competencies required to rapidly develop this cryo-tolerant IP. This would then be available under license for companies to create their own Cryo-CMOS chip solutions using it, turbo charging them with a competitive edge in the world of Quantum Computing.
The first step is accurately modelling how transistors work at these temperatures. This is being done by SemiWise and the QC research group at the University of Glasgow.
Synopsys will use the data generated to refine its TCAD tools. A combination of measurements and simulation data will be used by SemiWise to re-centre the foundry PDK for cryogenic temperatures and to enable the cryogenic circuit design.
As memory plays a key role in the electronics, this aspect is handled by sureCore, which is leading the project and whose expertise at keeping chip power consumption low will be vital to ensure that waste heat is kept to a minimum so it does not heat the chamber.
Chamber expertise is provided by Oxford Instruments which manufactures cryogenic systems.
Lastly, Universal Quantum and SEEQC represent end user needs and will determine what IP blocks the project will need to create for the Cryo-CMOS chips. Test chips will be characterised at the cryo temperatures to further refine and validate the models and IP.
