Cooler, denser chips?

The HP approach uses a nanoscale crossbar switch structure layered on top of conventional cmos, using an architecture which HP Labs researchers have named field programmable nanowire interconnect (FPNI). The research, by Greg Snider and Stan Williams (pictured), was conducted using classic modeling and simulation techniques. However, Williams said HP is working on producing an actual chip using the approach and believes it could have a laboratory prototype completed within the year. According to Williams: “Excessive heating and defective device operation arise at the nanoscale. What we’ve been able to do is combine conventional cmos technology with nanoscale switching devices in a hybrid circuit to increase effective transistor density, reduce power dissipation and dramatically improve tolerance to defective devices.” In the FPNI approach, all logic operations are performed in cmos, whereas most of the signal routing in the circuit is handled by a crossbar that sits above the transistor layer. Since conventional fpgas use 80 to 90% of cmos for signal routing, the FPNI circuit is much more efficient, the density of transistors used for performing logic is much higher and the amount of power required for signal routing is decreased. The researchers presented a ‘conservative’ chip model using 15nm wide crossbar wires combined with 45nm half pitch cmos. They believe the approach could be technologically viable by 2010 – three generations ahead of the International Technology Roadmap for Silicon without having to shrink the transistors.