Embedded FPGA technology to cut power in SoCs

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Looking to address demand for lower cost devices which consume less power when used in data centre, software defined radio and wireless infrastructure applications, Achronix has announced Speedcore. The embedded FPGA (eFPGA) IP, based on the same architecture deployed in its Speedster 22i FPGAs, can be integrated into a customer’s SoC.

Steve Mensor, vp of marketing, noted: “This is the biggest thing that Achronix has announced. The technology is already shipping to customers and we’re getting good feedback.”

Mensor noted there has been a lot of talk about FPGAs lately, mainly due to Intel’s acquisition of Altera. “All companies are looking at accelerator technology because data centre infrastructure is getting bogged down through the growth in data and security issues. FPGAs will dominate in applications such as unstructured search and Intel expects 30% of its Xeon processors will have FPGA acceleration integrated in the package or on die in the near future.”

According to Achronix, the concept of FPGA technology being embedded into other devices has been discussed for two decades, but has never been delivered.

Speedcore is said to deliver lower power by offering direct connection to the SoC and by sizing the FPGA element to the customer’s particular requirements. Higher interface performance reduces latency and, because the Speedcore element is smaller than a standalone FPGA, board size and layer count can be reduced. Other benefits are said to include isolation for noise immunity and ESD protection.

The company claims Speedcore could increase data bandwidth by a factor of 10, whilst reducing latency by a similar amount. Mansor added that power consumption could be 50% less, accompanied by a significant reduction in product cost.

Because Speedcore can be customised to the application’s exact requirements, the device can be smaller than if an FPGA was used. “The minimum size is 8000 LUTs,” Mansor said, “but our current customers are looking at a core ranging from 50,000 to 150,000 LUTs.”

With the IP targeted at a FinFET process – either TSMC’s 16FFT+ or Intel 14nm – Achronix has designed in what it calls ‘risk mitigation’. “FFT transistors age,” Mansor noted, “so we have included technology which makes them age uniformly.”

Mensor said Achronix expects Speedcore revenues to exceed $12million this year and to be more than $40m next year.