First IP core supporting the RapidIO 2.1 specification announced

According to Altera, the Serial RapidIO IP core supports up to four lanes at 5.0GBaud per lane and has been designed to address the increased bandwidth requirements of the wireless and military markets. The IP core is optimised for Stratix IV fpgas with embedded transceivers and is supported within Quarus II software v9.1. Altera claims that the RapidIO 2.1 specification enables increased performance up to 20GBaud in a range of applications, while support for the specification builds upon Altera's Serial RapidIO solution. This includes an end point IP core that is backward compatible to the RapidIO 1.3 specification, reference designs, application notes, test benches and interoperability reports with dsp and switch vendors. Luanne Schirrmeister, senior director of component product marketing at Altera, said: "Serial RapidIO is a popular interface for many of our wireless and military customers who put the utmost importance on system bandwidth and reliability. Combining the industry's first Serial RapidIO IP core supporting the 2.1 specification with Altera's industry leading fpga and transceiver technology solidly positions us to address our customer's most important system requirements, including performance, reliability and scalability."