FPGA based system supports 96million gate asic prototypes
1 min read
Taking advantage of the capacity of Virtex-7 2000T 3d fpgas, Aldec Europe has launched the HES-7, said to be a versatile asic/SoC prototyping system which lowers the cost of prototyping.
The HES-7 system feattures a high speed backplane connector that enables the expansion of custom daughter boards or the connection of up to four HES-7 boards. In the latter case, the system is capable of prototyping designs with up to 96million asic gates.
Zibi Zalewski, general manager of Aldec's hardware division, said: "Prototyping is beneficial to the whole asic delivery process and the most common way to prototype is to use fpgas. However, with most asic designs being between 10 and 20m gates, it has been necessary to employ several low density fpgas on one board; implementing the SoC/asic design has been a painful and costly process because the design needs to be partitioned between the multiple devices. Using a dual chip HES-7 prototyping solution reduces the design implementation effort and lowers the tool expense when supporting multimillion gate SoC designs."
HES-7 is available in four configurations, with capacities ranging from 4 to 96m asic gates.
