Green Hills' µ-velOSity RTOS has provided the software foundation for millions of resource-constrained systems since it was unveiled in 2006, covering a wide range of deployed IoT applications such as infusion pumps, disk drive controllers, wireless sensors, critical battery management systems, high speed communication modules, and automotive/industrial automation actuators.
Today’s IoT edge designs are increasing their use of RISC-V to execute time- and mission-critical software applications, often in SoCs where the RISC-V cores are combined with Arm or Intel CPUs on a single SoC. These heterogeneous mixed-core platforms are challenging to debug and optimise and often lead to developer productivity issues that can have a serious impact on product release schedules.
Green Hills Software’s µ-velOSity RTOS, middleware, hardware JTAG probe, combined with its MULTI development tools will provide a single integrated development environment that is purpose-built for debug and optimisation of heterogeneous processor SoC designs where the RISC-V core is either the main general-purpose CPU or is a secondary special-purpose acceleration core alongside the CPU..
“As the drive towards ever more complex multicore applications continues, the combination of security and safety – two similar but very different domains – into a single application, is enabled by our partners at Green Hills Software,” said Tim Morin, Technical Fellow and Marketing at Microchip Technology. “Having µ-velOSity and MULTI available for use by our mutual PolarFire SoC customers makes the development of these highly integrated applications a reality.”
According to Green Hills, the µ-velOSity RTOS’ simple, intuitive API for RISC-V together with its integrated middleware will save significantly on development time. When combined with the comprehensive, safety-certified, OS-agnostic MULTI development tools, developer productivity is increased, enabling customers to bring higher performing and more reliable products to the market much faster.
Key advantages of MULTI include a single dashboard to view the debugging of heterogenous cores in the SoC, kernel aware debugging, record-setting C/C++ compilers, MISRA-C adherence, and integrated code quality tools for stack performance and run-time errors.
